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4-8-1 Timer (HT66F50)

4-8-1 Timer (HT66F50). 利用 HT66F50 SIM 模組 單元中 PCK 腳位輸出特性 控制 speaker 發聲 SIM 串列界面模組. SIM 單元 2.8 串列界面模組. SPI (Master/Slave 傳輸界面 ) I 2 C ( 傳輸界面 ) PCK 腳位輸出特性 (SICM0 控制 ). SIM. 兩種傳輸介面 1 四線式 SPI(Master/Slave) 2 雙線式 I 2 C(Slave) 3 SIMD 為介面資料暫存器 (SPI,I 2 C) D[7:0]. SIMC0 控制暫存器.

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4-8-1 Timer (HT66F50)

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  1. 4-8-1 Timer (HT66F50) 利用HT66F50 SIM模組單元中PCK腳位輸出特性 控制speaker 發聲 SIM 串列界面模組

  2. SIM 單元 2.8串列界面模組 • SPI (Master/Slave 傳輸界面) • I2C (傳輸界面) • PCK腳位輸出特性(SICM0控制)

  3. SIM 兩種傳輸介面 1 四線式SPI(Master/Slave) 2 雙線式I2C(Slave) 3 SIMD為介面資料暫存器(SPI,I2C) D[7:0]

  4. SIMC0 控制暫存器 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN - Bit 7 6 5 4 3 2 1 0 Bit [7 6 5] = 000 , SPI master, fsys/4 = 001 , SPI master, fsys/16 = 010 , SPI master, fsys/64 = 011 , SPI master, fTBC = 100 , SPI master, TM0 CCRP Match freq./2 = 101 , Slave = 110 , I2C slave = 111 , 位定義

  5. SIMC0 控制暫存器 SIM2 SIM1 SIM0 PCKENPCKP1 PCKP0SIMEN - Bit 7 6 5 43 2 1 0 Bit [4] ;PCKEN = 1, enable PCK 輸出 = 0, disable PCK 輸出 Bit [3 2] ; PCKP[1:0] = 00 , PCK 輸出頻率 fsys = 01 , PCK 輸出頻率 fsys/4 = 10 , PCK 輸出頻率 fsys/8 = 11 , PCK TM0 CCRP Match freq./2 Bit [1] ;SIMEN =1 , 啟動 SIM模組 =0, 關閉SIM模組 BIT[0] ; 未使用

  6. TMnC0 控制暫存器(表2-5-12) TnPAU TnCK2 TnCK1 TnCK0TnONTnRP2 TnRP1 TnRP0 Bit 7 6 5 43 2 1 0 Bit [7] ; TnPAU = 1, 暫停計數 = 0, 繼續計數 Bit [6 5 4] ; TnCK2 TnCK1 TnCK0 = 000 , fINT= fsys/4 =100, fINT= fINT = 001 , fINT= fsys =101 ,保留 = 010 , fINT= fsys/16 =110 , fINT=TCKn = 011 , fINT= fsys/64 =111 , fINT= TCKn’ Bit [3] ;TnON =1 ,開始計數 =0,停止計數

  7. TMnC0 控制暫存器 TnPAU TnCK2 TnCK1 TnCK0TnONTnRP2 TnRP1 TnRP0 Bit 7 6 5 43 2 1 0 Bit [2 1 0 ] ; TnRP2 TnRP1 TnRP0 = 000 , 週期= 1024x fINT-1 =100,週期= 512x fINT-1 = 001 ,週期= 128x fINT-1 =101 ,週期= 640x fINT-1 = 010 ,週期= 256x fINT-1 =110 ,週期= 768x fINT-1 = 011 ,週期= 384x fINT-1 =111 ,週期= 896x fINT-1

  8. TMnC1 控制暫存器 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7 6 5 4 3 2 1 0 Bit [7 6] ; TnM1 TnM0 = 00 , 比對吻合輸出模式 = 01 , 未定義 = 10 , PWM = 11 , 計時/計數 Bit [0] ; TnCCLR =1, 當比較器A 比對吻合時清除計數器 =0,當比較器p 比對吻合時或計數器溢位清除計數器

  9. TMnC1 控制暫存器 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7 6 5 4 3 2 1 0 Bit [5 4] ; TnIO1 TnIO0 : Tpn_0,Tpn1 (輸出功能) 操作於 compare match, 比對吻合輸出模式時 TnM[1:0]=00) 00: 當比對吻合 輸出不變 10 ,當比對吻合 輸出 1 01: 當比對吻合 輸出 0 11 ,當比對吻合 輸出 轉態 操作於 PWM 模式時 TnM[1:0]=10) 00: 強制為非啟動, 01強制為啟動, 10 PWM輸出, 11未定義 操作於 Timer/Counter 模式時 TnM[1:0]=11, 無作用) Bit [0] ; TnCCLR =1, 當比較器A 比對吻合時清除計數器 =0,當比較器p 比對吻合時或計數器溢位清除計數器

  10. TMnC1 控制暫存器 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7 6 5 4 3 2 1 0 Bit [3] TnOC : Tpn_0,Tpn1 (輸出功能) 操作於 compare match, 比對吻合輸出模式時 TnM[1:0]=00) 1: 在首次比對吻前 輸出維持1 0: 在首次比對吻前 輸出維持0 操作於 PWM 模式時 TnM[1:0]=10) 1: 啟動準位1 0: 啟動準位0 Bit [2] ; TnPOL =1, 反向後再輸出 =0, 直接輸出

  11. ;PROGRAM : 4-8-1.ASM ;FUNCTION: Generate Tone by PCK O/P pin #INCLUDE HT66F50.INC ;-------------------------------------------------------------------- MY_DATA .SECTION 'DATA' ;== DATA SECTION == DEL1 DB ? DEL2 DB ? DEL3 DB ? INDEX DB ? ;-------------------------------------------------------------------- MY_CODE .SECTION AT 0 'CODE' ;== PROGRAM SECTION == ORG 00H ;HT-66F50 RESET VECTOR MOVE A,00001000B ; MOVE CP0C,A ;Disable Compactor 0 Function MOVE CP1C,A ;Disable Compactor 1 Function CLR ACERL ;關閉CP0, CP1比較器功能 , 將ADC設為I/O功能

  12. SET SIMC0 ; 規劃SIMC0暫存器 設為11111111 CLR TM0C0 ; 規劃TM0C0暫存器, T0CK=000 , fINT= fsys/4 MOV A,11000000B ;計時/計數 MOV TM0C1,A ; TnCCLR =0當比較器p 比對吻合時或計數器溢位清除計數器 MAIN: CLR INDEX ;比對吻合時之週期 LOOP: MOV A, TM0C0; AND A,11111000B; OR A,INDEX; MOVE TM0C0, A; T0RP[2:0]=INDEX SET TOON; 啟動 CTM 開始計數 0.25 sec MOV A, 25; CALL DELAY; CLR TOON; 停止 CTM 開始計數 0.25 sec MOV A,25; CALL DELAY;

  13. INC INDEX; SNZ INDEX.3; JMP LOOP; NO. JMP MAIN; Yes, restart DELAY PROC MOV DEL1,A ;SET DEL1 COUNTER DEL_1: MOV A,30 MOV DEL2,A ;SET DEL2 COUNTER DEL_2: MOV A,110 MOV DEL3,A ;SET DEL3 COUNTER DEL_3: SDZ DEL3 ;DEL3 DOWN COUNT JMP DEL_3 SDZ DEL2 ;DEL2 DOWN COUNT JMP DEL_2 SDZ DEL1 ;DEL1 DOWN COUNT JMP DEL_1 RET DELAY ENDP END

  14. ;********************************************************************;******************************************************************** ; Delay ;******************************************************************** DELAY PROC MOV DEL1,A ; DEL_1: MOV A,30; MOV DEL2,A; DEL_2 MOV A,110; MOV DEL3,A; DEL_3: SDZ DEL3; JMP DEL_3 ; SDZ DEL2 ; JMP DEL_2 ; SDZ DEL1 ; JMP DEL_1 ; RET ; DELAY ENDP END

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