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Single-wire Removal and Rectification Using Interpolant

Single-wire Removal and Rectification Using Interpolant. Speaker: Tai-Lin Chen Advisor: Chun-Yao Wang 2010/02/25. 1. Outline. Preliminaries Problem Formulation How to Rectify The Circuit After Removing Single Wire Future Work. 2. P. P q. A p  q. B ﹁ q  r.

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Single-wire Removal and Rectification Using Interpolant

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  1. Single-wire Removal and Rectification Using Interpolant Speaker: Tai-Lin Chen Advisor: Chun-Yao Wang 2010/02/25 1

  2. Outline Preliminaries Problem Formulation How to Rectify The Circuit After Removing Single Wire Future Work 2

  3. P P q A p q B ﹁ q r Craig Interpolation [Craig, 57] • Give a pair of formulas (A, B), if A  B= false, there exists an interpolant P for (A, B) such that: • A → P • P B = false • P refers only to common variables of A and B 3

  4. MT to Boolean Manipulation wt wt s-a-1 fault • The fault activation: • The set of minterms to cause the different value at wt between good circuit and bad circuit • ex: –fwt(X) • The fault propagation: • The set of minterms to propagate the different value to PO • ex: –ODCwt(X) 4

  5. MT to Boolean Manipulation a g1 b g3 c g2 d wt wt s-a-1 fault • MT(X) • The set of minterms can active the fault and propagate the fault. • MT(wt) = fault activation + fault propagation = -fwt(X)  –ODCwt(X) = {xxc’x, xxxd’}  {abxx} = {abc’x, abxd’} = {abc’x, abcd’} 5

  6. Redundancy Addition and Removal A circuit rewiring technique The objective is to add some redundant wires/gates such that a given target wire becomes redundant It will not change the functionality of the circuit

  7. Redundancy Addition and Removal Build up candidate set for the target wire <gs, v> = select from MA(wt) Redundancy tests on each candidate wire

  8. Example a g2 b target wire g1 c o1 d g3 g4 o2 e Add redundant wire(g1 → g4) can make wire(c → g2) become redundant

  9. Step of RAR D = extract dominator of wt = {g2, g3, g4} MA(wt) = {a=1, b=1, c = 0, d = 0, e =1, g1 = 0} Step1: Select gd from D, ex: g4 Step2: <gs, v> select from MA(wt), ex: <g1, 0> Step3: If v is controlling value of gd, wr = gs->gd Else, wr = inverter of gs->gd Step4: Test wr is redundant or not. If not, test next combination of gd and gs Step5: If find wr, connect wr and remove wt a g2 b target wire g1 c o1 d g3 g4 o2 e

  10. Two-way (one-stage) RAR Build up candidate set for the target wire Without redundancy tests

  11. Outline Preliminaries Problem Formulation How to Rectify The Circuit After Removing Single Wire (discuss) Future Work 11

  12. Problem Formulation • Give: • An arbitrarily target wire in a combinational circuit • Objective: • Remove single target wire, and functionality may change • Rectify the functionality by using interpolant 12

  13. Outline Preliminaries Problem Formulation How to Rectify The Circuit After Removing Single Wire Future Work 13

  14. 0/1 gt gd gs 1/0 gt gd gs How to Rectify The Circuit After Removing Single Wire v is the controlling value of gd wt • Similar to Two-way(one-stage) RAR method • MA(wt) -> <g, v>  • MA(gd) -> <g, -v>  14

  15. How to Rectify The Circuit After Removing Single Wire wt gt gd gs • Translate the problem into interpolant model • MA(wt) -> <g, 0> • MA(gd) -> <g, 1> • Find MT(X) through MA(X) • MT(wt) = -fwt(X)  -ODCwt(X)  -g(X) • MT(gd) = fgd(X)  -ODCgd(X)  g(X) 15

  16. How to Rectify The Circuit After Removing Single Wire onset onset offset offset = AND • If the fault at gd is 0/1 • Some minterms change its set from offset to onset • We append an AND gate gn at gd • MT(wt) -> -g(X) • MT(gn) -> g(X)

  17. How to Rectify The Circuit After Removing Single Wire • If the fault at gd is 1/0 • We append an OR gate gn at gd • MT(wt) -> g(X) • MT(gn) -> -g(X) • Rectified circuit is the interpolant of g(X) and –g(X)

  18. Example 0 0/1 a g1 g2 b 0 1 0/1 c 0 0/1 gd a g3 0 d MT(wt) = -g1(X)  -ODCg1(X) = { a’b’xx }  { a’xcx , xxcd’ } = { a’b’cx , a’b’cd’ } = { a’b’cx }

  19. Example a g1 g2 b c gn 1/0 1 gd a g3 d For fault 0/1, append an AND gate gn MT(gn) = gn(X)  -ODCgn(X) = { xbcx , axxd , axcx }  { xxxx } = { xbcx , axxd , axcx }

  20. Example a g1 g2 b c gn gd a g3 d MT(wt) = { a’b’cx }  -g(X) MT(gn) = { xbcx , axxd , axcx }  g(X) P -g g

  21. Example MT(wt) = { a’b’cx }  -g(X) MT(gn) = { xbcx , axxd , axcx }  g(X) K-map

  22. Example a b c gn gd a g3 d a+b K-map

  23. Outline Preliminaries Problem Formulation How to Rectify The Circuit After Removing Single Wire Future Work 23

  24. Future work Extend to multiple wires Other applications of interpolant Study 24

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