COMP 206: Computer Architecture and Implementation

Apr 02, 2013

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COMP 206: Computer Architecture and Implementation

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comp 206: computer architecture and implementation

2. Reading. Chapter 3: ILP and Its Dynamic ExploitationSection 3.1-3.3. 3. Dynamic Scheduling: Tomasulo's Algorithm. For IBM 360/91 (about three years after CDC 6600)Goal: High performance without special compilersDifferences between IBM 360 and CDC 6600 ISAIBM has only 2 register specifiers/instruction versus 3 in CDC 6600IBM has 4 FP registers versus 8 in CDC 6600Differences between Tomasulo Algorithm and ScoreboardControl and buffers distributed with Function Units versus centralized 9455

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2. Final Exam Review. Focus on materials after the midterm, includingPipelineExceptionsControl for Pipelined DatapathInstruction Level ParallelismScoreboardTomasula MethodCache

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2. Outline. Multiple-Issue ArchitecturesSuperscalar processorsVLIW (very long instruction word) processorsSchedulingStatically scheduled (using compiler techniques)Dynamically scheduled (using variants of Tomasulo's alg.)Reading: HP4, Sections 2.6-2.10. 3. Multiple Issue. Eliminating data a

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COMP 206: Computer Architecture and Implementation

2. Outline. IntroductionDRAM OrganizationChallengesBandwidthGranularityPerformanceReading: HP3 5.8 and 5.9. 3. Basics of DRAM Technology. DRAM (Dynamic RAM)Used mostly in main mem.Capacitor 1 transistor/bitNeed refresh every 4-8 ms5% of total timeRead is destructive (need for write-

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COMP 206: Computer Architecture and Implementation

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COMP 206: Computer Architecture and Implementation

2. Outline. Course InformationLogisticsGradingSyllabusCourse OverviewTechnology TrendsMoore's LawThe CPU-Memory Gap. 3. Course Information (1). Time and PlaceMW 2:00-3:15pm, Sitterson Hall 011InstructorMontek Singhmontek@cs.unc.edu (not singh@cs!)SN 245, 962-1832Office hours: MW 3:1

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COMP 206: Computer Architecture and Implementation

2. Ensembles of Disks. Key ideaUse collection of disk drives to improve characteristics of disk systems (storage capacity, bandwidth, etc.)Used in mainframes for a long timeRAIDRedundant Array of Inexpensive Disks (original 1988 acronym)Redundant Array of Independent Disks (redefined in 1992).

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COMP 206: Computer Architecture and Implementation

2. Outline. Quantitative Principles of Computer DesignAmdahl's law (make the common case fast)Performance MetricsMIPS, FLOPS, and all that?Examples. 3. Example 1 (see HP3 pp. 42-45 for more examples). Which change is more effective on a certain machine: speeding up 10-fold the floating point sq

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COMP 206: Computer Architecture and Implementation

2. Reading. Appendix A (Crosscutting Issues). 3. What is a Scoreboard?. A Scoreboard is a table maintained by the hardware:keeps track of instructions being fetched, issued, executed etc.keeps track of the resources (functional units and operands) they use/needkeeps track of which instructions mo

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COMP 206: Computer Architecture and Implementation

2. Outline. Cache CoherenceReading: HP3 Section 6.3

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Architecture, Implementation, and Testing. Architecture and Implementation Prescriptive architecture vs. descriptive architecture Prescriptive architecture: designed architecture, to be implemented by code into an executable system

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Pipelined Implementation CSCi 2021: Computer Architecture and Organization. Chapter 4.4, 4.5 (through 4.5.7). Today. Pipelining Performance Hazards Deviate a bit from the slides (defer branch prediction). Last Time. Sequential processor implementation Instruction execution. Idea

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COMP 206: Computer Architecture and Implementation

COMP 206: Computer Architecture and Implementation. Montek Singh Wed, Nov 16, 2005 Topic: Main Memory (DRAM) Organization. Outline. Introduction DRAM Organization Challenges Bandwidth Granularity Performance Reading: HP3 5.8 and 5.9. Basics of DRAM Technology. DRAM (Dynamic RAM)

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Pipelined Implementation CSCi 2021: Computer Architecture and Organization

Pipelined Implementation CSCi 2021: Computer Architecture and Organization. Chapter 4.5 (through 4.5.7). Today. Last Time. Idea Divide process into independent stages Move objects through stages in sequence At any given times, multiple objects being processed. Parallel. Sequential.

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Sequential Implementation CSCi 2021: Computer Architecture and Organization

Carnegie Mellon. Carnegie Mellon. Sequential Implementation CSCi 2021: Computer Architecture and Organization. Chap. 4.3. Last Time. Hardware logic design concepts Boolean algebra, logic units, building blocks HCL. Carnegie Mellon. Today. Sequential processor implementation

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COMP 530 Database Architecture and Implementation. 1. Introduction. Why Learn DBMS?. You want to find a JOB !!!. Big Names in Database Systems. Web data management. Who Needs Database Systems. Typical Applications: Personnel management Inventory and purchase order

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COMP 4300 Computer Architecture Datapath. Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu. Fall, 2010. Datapath for Branch Instructions. beq rs, rt, offset. if (R[rs] == R[rt]) then PC ← PC+4 + s_extend(offset<<2). Datapath: More Detailed View.

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Prof. Emin G ün Sirer Fall 2007 Koç University. COMP 303 Computer Architecture. Course Objective. Bridge the gap between hardware and software How a processor works How a computer is organized How to program at the hardware level Establish a foundation for building higher-level programs

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implementation and architecture support. UIMS user interface management systems OO style models PAC/MVC UIDE user interface development environments Toolkits . UIMS tradition interface layers. linguistic: lexical/syntactic/semantic Seeheim: Arch/Slinky. Seeheim model. what’s this?.

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