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Achieving Signal and Timing Requirements for a DDR2 Based System

Achieving Signal and Timing Requirements for a DDR2 Based System. Kim Owen, Bruce Caryl Application Engineers Mentor Graphics. DDR2 Presentation Overview. DDR2 Technology Review Planning DDR2 Topology and Entering Constraints Review Routing Guidelines

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Achieving Signal and Timing Requirements for a DDR2 Based System

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  1. Achieving Signal andTiming Requirements fora DDR2 Based System Kim Owen, Bruce Caryl Application Engineers Mentor Graphics

  2. DDR2 Presentation Overview • DDR2 Technology Review • Planning DDR2 Topology and Entering Constraints • Review Routing Guidelines • Verifying SI and Timing Margins Using the Hyperlynx 8.0 DDR/2/3 Wizard BC-KO, U2U, Nov 2008

  3. DDR2 Overview • What is DDR2, anyway? • DDR2 = “Double-Data-Rate v2” synchronous DRAM memory • Physically, it’s a source-synchronous technology • Small groups of data (or “byte lanes”) have their own “private” clocks or strobes Each 8-bit lane gets its own strobe BC-KO, U2U, Nov 2008

  4. DDR2 Overview • Data bandwidth is doubled by clocking data on every edge of the strobe (rising and falling) • DDR2 is popular, because it’s cheap and fast: • JEDEC spec supports 400, 533, 667, 800,and 1066 Mbps • x64 bits  8.528 GBps ©2003 Micron Technology, Inc. All rights reserved. BC-KO, U2U, Nov 2008

  5. ©2003 Micron Technology, Inc. All rights reserved. DDR2 Bus Architecture BC-KO, U2U, Nov 2008

  6. Strobe Data New for DDR2 Technology • DDR2 Operating Speeds • DDR2-400 (200 MHz clock) • DDR2-533 (266 MHz clock) • DDR2-667 (333 MHz clock) • DDR2-800 (400 MHz clock) • Source-Synchronous interface like original DDR • Recommended board impedance is 50 ohms DQS DQ0 DQ1 DQ2 DQS DQ0 DQ1 DQ2 Strobe Data BC-KO, U2U, Nov 2008

  7. Technical Background • DDR2 timing margins are so tight, signal-integrity and timing calculations are critical • @ 800 Mbps rate, the bit period is only 1.25 ns • This means previous bits linger on the copper bus even while later bits are being sent • An effect called “intersymbol interference” (ISI) • Each bit’s shape and timing depends previous bits Bits are interfering with each other  ISI, and therefore the shape of each bit is different  different timing There is no longer a single delay: Every bit delay varies at least a little on every clock cycle! BC-KO, U2U, Nov 2008

  8. NEW: DDR2 Signaling – Example SSTL-1.8 VDDQ (1.8V nominal) VOH(MIN) VIH 1.025V 0.9V AC 1.150V VIH DC 0.775V VI L DC VIL 0.650V AC Receiver VOL (MAX) VSSQ Transmitter

  9. NEW: DDR2 On Die Termination • ODT – On Die Termination • Built into the controller IC and DDR2 SDRAM • Selectable resistor values • 50 Ohm, 75 Ohm, 150 Ohm • ODT turns on / off depending on Read or Write operation * Courtesy of Micron BC-KO, U2U, Nov 2008

  10. BC-KO, U2U, Nov 2008

  11. On Die Termination New: BC-KO, U2U, Nov 2008

  12. BC-KO, U2U, Nov 2008

  13. ODT Values must be chosen and specified for Simulation BC-KO, U2U, Nov 2008

  14. NEW: DDR2 Delay Measurement • Slew Rate affects switching time Charge Model Simplification: The area under the curve affects when the buffer switches + Dt - Dt Vih AC 2 V/ns 1 V/ns 0.5 V/ns Vref BC-KO, U2U, Nov 2008

  15. Setup Nominal Slew Rate New Measurement Requirement

  16. Setup Tangent Line Slew Rate New Measurement Requirement

  17. Clock Derating Table tIS (total setup time) = tIS (base) + ΔtIS (derating) tIH (total hold time) = tIH (base) + ΔtIH (derating) Derating can consume 50% of your Interconnect Timing Budget!

  18. 533 MBS DDR2 Write Timing Budget Pre-Route planning and constraint management is essential BC-KO, U2U, Nov 2008

  19. DDR2 Planning and Constraints BC-KO, U2U, Nov 2008

  20. DDR2 Design Guidelines • What results are important • We need to constrain 4 critical lengths • Net length from the controller to the 1st DIMM slot • Net length between DIMM slots • Net length from lastslot to the pull-up term.(only Address/Command) • All DQS/DQ groups should be length matched to minimize skew within the group and across the channel VDD VTT #1 #2 #3 MemoryController DIMM Slot 1 VTT Pull-up Resistors DIMM Slot 2 BC-KO, U2U, Nov 2008

  21. DDR2 Design Guidelines • Spacing Recommendations • Varies depending on stackup • Typically rules of thumb say 3H spacing • For a 5 mil dielectric this would be 15 mils • For signals coupled closely to reference planes, often 1.5H can be used or ~8 mils BC-KO, U2U, Nov 2008

  22. Mentor DDR2 Design Kit • Design kits for DDR2 are available online through SupportNet http://supportnet.mentor.com/reference/other-info/hyperlynx_designkits/downloads.cfm • Design kits include presentations and example LineSim schematics with typical DDR2 memory board topology BC-KO, U2U, Nov 2008

  23. Key Signal Groups • Address/Command (A, BA, RAS#, CAS#, WE#) • Single ended, parallel, terminated to VTT (0.9V), registered on rising edge of clock • May use 2T timing if too heavily loaded • Control (S#, CKE, ODT) • Single ended, parallel, terminated to VTT (0.9V), registered on rising edge of clock • Each bank has own control signal (less loading) • Must use 1T timing • Clocks • Differential , terminated on die with ODT • Data • Single ended, bi-directional, synchronized to Data Strobes, terminated on die with ODT • Data Strobes • Differential, bi-directional, terminated on die with ODT • Can be single ended but differential more commonly used • One diff pair for each byte lane BC-KO, U2U, Nov 2008

  24. DIMM Layout • Address/Command (A0) • Data (DQ0) BC-KO, U2U, Nov 2008

  25. DIMM Layout • Clock (CK0) • Data Strobe (DQS8) BC-KO, U2U, Nov 2008

  26. Power Supplies • Three power supplies are required • VDD 1.8 V Supply for I/O Drivers (SSTL1.8) and DRAM core • Controller core may have additional requirements • VREF 0.9 volt switching reference voltage used by DRAMs and controller • Critical value since all switching is referenced to VREF • Isolate and/or shield with ground • VTT 0.9 volt termination supply (1/2 VDD) • Use wide island trace area • +/- 2% AC noise • VTT = VREF +/- 40 mV • VREF and VTT should be properly decoupled • VREF is more sensitive to noise, so it cannot share the VTT plane BC-KO, U2U, Nov 2008

  27. Constraint Entry System (CES) • Use CES to fully constrain all important aspects of a net • Trace width, impedance, layer, clearance, min/max delay, matching, diff pair rules, etc. • Constrain one net in bus, create a constraint template, apply template to all other nets in bus • Constraints are used by Auto Router and manual routing • Constraints can be entered from schematic or layout (synchronized during forward and back annotation) • Allows engineering to create verifiable requirements • Ensures implementation matches requirements BC-KO, U2U, Nov 2008

  28. Address/Command/Control Signals Single ended, parallel bus architecture Synchronized to memory clock Switch on positive edge of clock Terminated to VTT (0.9V) Address/Command Can have heavy capacitive loading (36 DRAMS in 2 DIMM configuration) Control signals have separate signal for each bank (1/4 the load in 2 DIMM configuration) For DDR2-667 (333 MHz clock), Address changes at 167 MHz max (1T Timing) BC-KO, U2U, Nov 2008

  29. Address Topology Simplified Model trace lengths, widths, layers, termination, timing Create constraints for layout Use intended board stackup Length of trace to terminator Length of trace between connectors Stackup DIMM modeled as EBD (Electrical Board Desc.) Length of trace on PCB BC-KO, U2U, Nov 2008

  30. Address Simulation (1T Timing) • 36 DRAM loads • Waveforms at 4 DRAMS • Marginal signal quality • Limited timing budget BC-KO, U2U, Nov 2008

  31. Improving Address/Command Quality and Timing • Provide a separate (duplicate) signal driver for each DIMM at the controller • Use 2T timing to allow two clock cycles per address change • Add a compensation capacitor for each signal (18-27pF recommended) • Only recommended for > 18 memory chip loads BC-KO, U2U, Nov 2008

  32. Address Simulation (2T Timing) • 36 DRAM loads • Waveforms at 6 DRAMS • Improved signal quality • Ample timing budget BC-KO, U2U, Nov 2008

  33. Address Constraints • Controller to first DIMM max = 3200 th • First DIMM to second DIMM max = 650 th • Second DIMM to terminator max = 600 th • All Address lines matched to 200 th • All Address lines matched to CK_N0 to 5mm (200 th) • Prevents clock-to-address skew • Sometimes implemented as average of clock lengths BC-KO, U2U, Nov 2008

  34. Address Constraints in CES BC-KO, U2U, Nov 2008

  35. Command/Control Constraints in CES BC-KO, U2U, Nov 2008

  36. Clock Signals • Differential Signals • On die termination (ODT) is used • AC compensation cap recommended for DIMMs • Three clock pairs per DIMM when using unbuffered DIMMs BC-KO, U2U, Nov 2008

  37. Clock Topology Connector DIMM Breakout Length of trace on PCB BC-KO, U2U, Nov 2008

  38. Clock Topology with Vias and AC Compensation RAM Model • Model via transitions • Model of compensation cap • Provide complete constraint data • Lengths • Route layers • Via types BC-KO, U2U, Nov 2008

  39. Clock Topology without AC Compensation • Waveform at all receivers • No compensation cap • Multiple transitions on rcv6 • Poor overall signal quality BC-KO, U2U, Nov 2008

  40. Clock Topology with AC Compensation • Waveform at all receivers • 10pF compensation cap • Good signal quality • Clean transitions BC-KO, U2U, Nov 2008

  41. Clock Constraints • Controller to DIMM max = 3900 th • DIMM to AC compensation max = 600 th • Clock diff pair match = 25 th • “Clock Differential Pairs” Net Class • Inner Layer Routing (layers 3, 5) • Often specified to be routed on same layer • 4 mil trace width with 4 mil spacing • Coupling may vary based on stackup • 100 ohm differential impedance BC-KO, U2U, Nov 2008

  42. Clock Constraints in CES BC-KO, U2U, Nov 2008

  43. Data (DQ) Signals • Single ended nets • On die termination (ODT) is used • Must be matched tightly to data strobes (DQS) • Must be matched between byte lanes (8 bit groups) • For write operation: • DIMM receiving data is set to 150 ohm ODT • DIMM not receiving data is set to 75 ohm ODT • For read operation • Controller is set to 150 ohm ODT • DIMM supplying data is set to open • DIMM not supplying data is set to 75 ohm ODT BC-KO, U2U, Nov 2008

  44. Data (DQ) Topology DIMMs BC-KO, U2U, Nov 2008

  45. Data (DQ) Simulation • Waveform DIMM1 front, write • DIMMS set to 150 ohm ODT • No eye opening BC-KO, U2U, Nov 2008

  46. Data (DQ) Simulation • Waveform DIMM1 front, write • DIMM2 set to 75 ohm ODT • DIMM1 set to 150 ohm ODT • 680 ps eye opening, 3% jitter BC-KO, U2U, Nov 2008

  47. Data (DQ) Constraints • Controller to DIMM max = 3900 th • DIMM X1 to DIMM X2 max = 650 th • Match to all other DQ signals in byte lane • Tolerance = 100 th • Match to corresponding DQS • Tolerance = 100 th • “DQ Data” Net Class • Can be layer restricted • Due to matching with DQS, DQ is also matched to CK_N0 +/- 25 mm (1 inch) • Results in Byte Lanes matching to 1 inch BC-KO, U2U, Nov 2008

  48. Data (DQ) Constraints in CES BC-KO, U2U, Nov 2008

  49. Data Strobe (DQS) Signals • Differential signals • On die termination (ODT) is used • Must be matched tightly to associated data group • Data is clocked in on both edges • Must be matched between byte lanes (8 bit groups) • Must be matched to Clocks within +/- 25 mm BC-KO, U2U, Nov 2008

  50. Data Strobe DQS Topology DIMM DIMM Connectors BC-KO, U2U, Nov 2008

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