CS 6461: Computer Architecture Instruction Set Architecture

1. CS 6461: Computer ArchitectureInstruction Set Architecture Instructor: Morris Lancaster

2. Appendix A+ Instruction Set Principles and Examples

3. ?Design a New High Performance System? • ISA • What instructions should we include • Internal Organization • How do the instructions implemented affect the internal organization (and subsequently performance) • How best approach this problem? • Understand what a computer and an instruction set architecture does for us • Look at current architectures for insight CS 6461 Instruction Set Architecture

4. Classifying ISA’s • Type of Internal Storage • Stack • Accumulator • Set of Registers CS 6461 Instruction Set Architecture

5. Operand Locations for 4 ISA Classes CS 6461 Instruction Set Architecture

6. Design Decisions • Instruction Set Architecture Class (Load-Store?) • How Many Registers (more is good) • How Many Operands in the instruction? CS 6461 Instruction Set Architecture

7. Code Sequences for the 4 Classes • Since 1980s almost all new designs are load store architectures. • Machines have large register files • Registers are easier for the compiler to manage (addressed in only one way) CS 6461 Instruction Set Architecture

8. Number of Memory Addresses CS 6461 Instruction Set Architecture

9. Tradeoffs for the ISA Classes CS 6461 Instruction Set Architecture

10. Memory Addressing(page B9) • Register Add R4,R3 R4<- R4 + R3 • Immediate Add R4,#3 R4<- R4 + 3 • Displacement Add R4,100(R1) R4<- R4 + Mem[100+R1] • Register Indirect Add R4,(R1) R4<- R4 + Mem[R1] • Indexed Add R3,(R1+R2) R3<- R3 + Mem[R1+R2] • Direct Add R1, (1001) R1<- R1 + Mem[1001] • Memory Indirect Add R1, @(R3) R1<- R1 + Mem[Mem[R3]] • AutoIncrement Add R1, (R2)+ R1<- R1 + Mem[R2] R2<- R2 +d • AutoDecrement Add R1, -(R2) R2<- R2 - d R1<- R1 + Mem[R2] • Scaled Add R1, 100(R2)[R3] R1<- (R1) + Mem[100+(R2) + (R3)*d] CS 6461 Instruction Set Architecture

11. Summary of Use of Addressing Modes for DEC VAX Architecture CS 6461 Instruction Set Architecture

12. Displacement Values Are Widely Distributed CS 6461 Instruction Set Architecture

13. About ¼ of Data Transfers and ALU Operations Have an Immediate Operand CS 6461 Instruction Set Architecture

14. Distribution of Immediate Values CS 6461 Instruction Set Architecture

15. Type and Size of Operands • 8, 16, 32, 64 bits • Alignment • Fetch capability • Encoding type CS 6461 Instruction Set Architecture

16. Distribution of Data Access By Size CS 6461 Instruction Set Architecture

17. Control Flow • Addressing modes • Conditional branch operations • Frequency distributions CS 6461 Instruction Set Architecture

18. Breakdown of Control Flow Instructions CS 6461 Instruction Set Architecture

19. Branch Distance In Number of Instructions CS 6461 Instruction Set Architecture

20. Frequency of Different Types of Compares in Conditional Branches CS 6461 Instruction Set Architecture

21. Fig 2.38 Data Reference Sizes CS 6461 Instruction Set Architecture

22. Fig 2.23 Three Variations In Instruction Encoding CS 6461 Instruction Set Architecture

23. Instruction Encoding • Balance • Desire to have as many registers and addressing modes as possible • The impact of the size of the register and addressing mode fields on the average instruction size and hence average program size • A desire to have instructions encoded into lengths that will be easy to handle in a pipelined implementation CS 6461 Instruction Set Architecture

24. The Role of Compilers • Structure • Optimizations • Register Allocation (tied with hardware) • Impact of Compiler Technology on Architects Decisions CS 6461 Instruction Set Architecture

25. Fig 2.24 Compiler Structure CS 6461 Instruction Set Architecture

26. Fig 2.26 Change in Instruction Count From Compiler Optimization (SPEC2000) CS 6461 Instruction Set Architecture

27. MIPS Instruction Set • MIPS 64 has 32 general purpose registers of 64 bits in length (R0…R31) • Value of R0 is always 0 • 32 floating point registers capable of holding 32 or 64 bit floating point numbers • Instruction formats • I type immediate • R type register-register • J type jump CS 6461 Instruction Set Architecture

28. MIPS Instruction Set • Instruction nomenclature • Opcode • Registers rs, rd, rt CS 6461 Instruction Set Architecture

29. Fig 2.27 MIPS Instruction Layout CS 6461 Instruction Set Architecture

30. Fallacies and Pitfalls • Pitfall – Designing a “high-level” instruction set feature specifically oriented to supporting a high-level language structure. • Fallacy – There is such a thing as a typical program • Pitfall – Innovating at the instruction set architecture to reduce code size without accounting for the compiler. • Fallacy – An architecture with flaws cannot be successful • Fallacy – You can design a flawless machine CS 6461 Instruction Set Architecture