Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs

1. Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs Hao Yu, Joanna Ho and Lei He Electrical Engineering Dept. UCLA Partially supported by NSF and UC-MICRO fund from Intel

2. New Solution for High-performance Integration • 2D SoC has limited device density and interconnect performance (delay) • Potential solution: 3D Integration • Fabrication Technologies: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth • Extra challenges: thermal integrity and power integrity

3. 40c 70c 100c 130c 160c Thermal Challenge in 3D ICs • Inter-layer dielectrics are poor thermal conductors • the temperature of each die increases along third dimension, where the heat sink is on the top • High temperature affects interconnect and device reliability and brings variations to timing • Vertical vias are good thermal conductors • They can be used as thermal vias to remove the heat from each die

4. Power Delivery Challenge in 3D ICs • The voltage bounce is significant in P/G planes at the bottom due to resonance • Large voltage bounce affects the performance of I/Os • Vertical vias can minimize the returned current path and hence loop inductance • They can be used as power vias to reduce the voltage bounce for each P/G plane

5. Motivation • Staple vias from the top heat-sink to the bottom P/G planes • remove heat in silicon die and reduce voltage bounce in package plane • Too many? -> signal routing congestion • Too few? -> reliability by current density • Primary contributions of our work • Formulate a levelized via stapling to simultaneously minimize both temperature hotspot and voltage bounce • Develop an efficient sensitivity-driven optimization with use of structured and parameterized macromodel Via Planning Problem in 3D IC • Previous work (thermal via planning) • Iterative via planning during placement [Goplen-Sapatnekar:ISPD’05] • Alternating-direction via planning during routing [Zhang-Cong:ICCAD’05] • Both use steady-state thermal analysis and ignore variant thermal power • Both ignore that the vertical via can be also designed to remove the voltage bounce in power supply

6. Outline • Modeling and Problem Formulation • Integrity Analysis and Sensitivity based Optimization • Experimental Results • Conclusions

7. Electric and Thermal Duality • Both electric and thermal systems can be described in MNA (modified nodal analysis)

8. Two Distributed Networks for 3D IC • All device/dielectric layers and power planes are discretized into tiles • A distributed electrical RLC model for power/ground plane • A distributed thermal RC model for device/dielectric layer • Each via is modeled by a RC pair

9. Steady-state thermal model and analysis Tiles connected by thermal resistance Heat sources modeled as time-invariant current sources Steady-state temperature can be obtained by directly solving a time-invariant linear equation Thermal Model and Analysis • Transient thermal model and analysis • Tiles connected by thermal resistance and capacitance • Heat sources modeled as time-variant current sources • Transient temperature can be obtained by directly solving a time-variant linear equation

10. Need of Transient Thermal Modeling • Time-variant workload and dynamic power management introduce temporal and spatial thermal power variation • Thermal power is the runtime average of cycle-accurate power over thermal time-constant • Thermal power decides temperature • Steady-state analysis needs to assume a maximum thermal power simultaneously for all regions • But it rarely happens and hence can result in an over-design • Direct transient analysis is accurate but time-consuming • It calls for more accurate yet efficient transient thermal modeling during the design automation

11. Need of Simultaneous Thermal/Power Co-Design • Temperature hotspots usually distribute differently from voltage bounce • A thermal integrity map tends to result in a uniform via stapling pattern • A power integrity map tends to result in a biased via stapling pattern in center • Considering thermal and power integrity separately may also lead to over-design

12. Via Stapling • Minimize via number under thermal/power integrity constraint D0 D1 D2 • Di levelized via density • ni via number at different level • Vmax power integrity constraint • Tmax thermal integrity constraint • Dmax congestion from signal via • Dmin current density constraints Problem Formulation • A levelized via stapling is used • Each level has a different via density Di • It can be efficiently solved by a sensitivity based optmization • The sensitivity is calculated from a structured and parameterized macromodel

13. Outline • Modeling and Problem Formulation • Integrity Analysis and Sensitivity based Optimization • Experimental Results • Conclusions

14. 1 2 3 4 5 6 7 8 8 4 7 3 0 1 - 1 1 5 2 6 0 0 X(2,6)= 1 2 3 4 5 6 7 8 0 1 -1 0 0 • Both Di and Xi are parametrically added into the nominal MNA equation Parameterized System Equation • The levelized stapling pattern is described by adjacent matrix X • Via conductance gi and capacitance ci are both proportional to the area Dior density (Di/a) (a is unit via area)

15. Expand state variablesx(D1,…DK,s)by Taylor expansion w.r.t. toDi[Li-Pileggi:ICCAD’05] • Construct a new state variables by nominal values and sensitivities • Expanded system is reorganized into a lower-triangular-block system Separation of Nominal and Sensitivity • Since system size is enlarged, we can reduce it by model reduction

16. … … Small but dense Macromodel by Model Reduction project small size large size • Model reduction can reduce model size and preserve accuracy by matching moments of inputs[Odabasioglu-Celik-Pileggi:TCAD’98] • The projection above is non-structured, and will mess the nominal values and their sensitivities again • This can be solved by a structure-preserving reduction [Yu-Tan-He:BMAS’05, Yu-Shi-He:DAC’06]

17. Structured projection can result in a reduced system with preserved structure • Nominal values and sensitivities are still separated after reduction • There is only one LU-factorization of the reduced G0in diagonal Structured Projection (I) • Block-diagonally partition the flat projection matrix according to the size of nominal state-variable and sensitivity

18. Direct sensitivity calculation Time-domain Analysis • Nominal response and sensitivity can be solved separately and efficiently with BE in time-domain • Generated sensitivities can be used in any gradient based optimization We call this method as SP-MACRO

19. Update Density Vector Check Integrity Constraints Calculate T/V nominal+sensitivity • Structured and parameterized reduction provides an efficient calculation of both nominal value and sensitivity • The via density vector D can be efficiently updated during each iteration • Normalized sensitivity according to both temperature and voltage (T/V) sensitivities Sensitivity based Optimization • Via optimization flow • Further speedup: adjoint Lagrangian method similar to [Visweswariah-Conn-Haring:TCAD’00]

20. Outline • Modeling and Problem Formulation • Integrity Analysis and Sensitivity based Optimization • Experimental Results • Conclusions

21. Experiment Settings • A modest 3D stacking

22. Accuracy of Reduced Macromodel • Transient voltage responses of exact and MACRO models at ports 1 and 5 in one P/G plane with step-response input • The responses of macromodels are visually identical to those exact models but with >100 speedup

23. Temperature/Voltage Reduction during OPT • The T/V are both decreased iteratively • The allocated via results in a design meeting the targeted temperature 52C and the voltage bounce 0.2V

24. Steady-state vs. Transient • Transient thermal analysis reduces via by 11.5% on average compared to using steady thermal analysis • Our SP-Macro results in an efficient transient analysis that reduces runtime by 155X compared to the direct steady-state analysis

25. Sequential vs. Simultaneous • Simultaneous optimization reduces via by 34% on average compared to the sequential optimization • Comparisons of via distribution at different levels for ckt (27740)

26. Conclusions • Vertical vias play a critical role in 3D IC design • A simultaneous thermal and power integrity driven via planning • It saves via number by 34% on average compared to a sequential design • A structured and parameterized macromodel can be efficiently employed during the design optimization • This method can be further extended • 3D signal and P/G routing • Performance driven 3D design

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