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Project D02209: FPGA Bridge between High Speed Channel & External Network

High Speed Digital Systems Lab. Project D02209: FPGA Bridge between High Speed Channel & External Network. Mid Semester Presentation 30/05/10. Supervisor: Mony Orbach Students: Alex Blecherov Eyal Ben Dov Project Period: 2 semesters. High Speed Digital Systems Lab.

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Project D02209: FPGA Bridge between High Speed Channel & External Network

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  1. High Speed Digital Systems Lab Project D02209:FPGA Bridge between High Speed Channel & External Network Mid Semester Presentation 30/05/10 Supervisor: Mony Orbach Students: Alex Blecherov Eyal Ben Dov Project Period: 2 semesters

  2. High Speed Digital Systems Lab Motivation Utilizing High-speed communication between devices Narrowing the gap between High-speed LAN (via FSB) and External network (via Internet) Demand for reliable and fast communication

  3. High Speed Digital Systems Lab General Conception Assuming there are several different large networks – Internal Fast Networks and External Networks (slower ones), we wish to create a mutual environment (to act as an accelerator) to provide the ability to communicate between them with high rates.

  4. High Speed Digital Systems Lab Goals Design & implementation of high speed communication bridge on Xilinx FPGA device (using SoPC) Allowing Local and External networks which operate with different protocols and rates to communicate with each other Achieving fastest transmission rate possible Explore and expertise a new FPGA device & work environment

  5. High Speed Digital Systems Lab Specifications Hardware • Xilinx Virtex-6 ML605 FPGA Evaluation Kit Software • ISE Design Suite Logic Edition Version 12.1 • LogiCore Generator • XPS • ISIM / Modelsim

  6. High Speed Digital Systems Lab Possible Solutions Solution 2 Solution 1 Local Fast Networks (up to 6 Gb/ps) Local Fast Networks (up to 6 Gb/ps) External Network (TCP/IP) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Bridge: Virtex 6 ML605 FPGA

  7. Chosen Solution High Speed Digital Systems Lab External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA Local Fast Networks (up to 6 Gb/ps)

  8. Project Test Bench Diagram High Speed Digital Systems Lab Local Fast Network (up to 6 Gb/ps) External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA

  9. Sem. A Test Bench Diagram High Speed Digital Systems Lab Internal Loopback External Network (TCP/IP) Bridge: Virtex 6 ML605 FPGA

  10. Overview of the Protocols in use High Speed Digital Systems Lab • FSB (Internal Network) will use the Aurora protocol – IP Core. • External Network will use the TCP Internet Protocol over Ethernet.

  11. Tri Mode Ethernet MAC PacketBased on IEEE Std 802.3 High Speed Digital Systems Lab 64 – 1518 Bytes • Preamble – Exists due to historical reasons,contains the constant pattern 0x55 [optional]. • SFD - Marks the start of the frame, and must contain the value 0xD5. • Destination Address - The LSB determines if the address is an individual/unicast (0) or group/multicast (1) address. • It’s the first field that must always be provided.

  12. Tri Mode Ethernet MAC PacketBased on IEEE Std 802.3 High Speed Digital Systems Lab 64 – 1518 Bytes • Source Address – Must always be provided by the client because it’s not modified by the Ethernet MAC. • Length/Type – If the decimal value of this field is 1536 or greater it’s interpreted as a Type field (Indicates if it’s a VLAN frame or PAUSE/MAC ctrl frame). Otherwise it’s interpreted as a Length field and represents the number of bytes in the following Data field.

  13. Tri Mode Ethernet MAC PacketBased on IEEE Std 802.3 High Speed Digital Systems Lab 64 – 1518 Bytes • Data – Varies from 0-1500 Bytes, must always be provided. • Pad – Used to ensure that the frame length is at least 64 bytes in length, and required for successful CSMA/CD • operation. • FCS - Calculated over the destination address, source address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC). If an incorrect FCS value • is received it indicates that the received frame is bad.

  14. Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 High Speed Digital Systems Lab • Version – For IPv4, this has a value of 4. • Internet Header Length (IHL)  - Specifies the size of the header (5-15). • Differentiated Services – Type of Service - Indicates how this packet should be treated. • Total Length - Defines the entire datagram size (576 - 65,535Bytes).

  15. Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 High Speed Digital Systems Lab • Identification ,Flags & Fragment Offset – Used to handle received fragmented packet. • Time To Live (TTL) - Indicates how many hops are allowed before the packet is discarded. • Protocol - Defines the protocol used in the data portion of the IP datagram

  16. Internet Protocol Suite (TCP/IP) Packet – IETF – RFC 791 High Speed Digital Systems Lab • Header Checksum - Used for error-checking of the header (calculated every hop). • Source & Destination Address – An IPv4 address is a group of four octets for a total of 32 bits. • Options - Additional header fields that may follow the destination address field, but usually not in use.

  17. Overview of the Cores in use High Speed Digital Systems Lab • TEMAC (Tri-Mode Ethernet MAC) - The TEMAC core is designed to the IEEE 802.3 (Ethernet protocol) specification and operates in 1000Mbps, 100 Mbps, and 10 Mbps modes. • We’ll use this core for the External network. • Aurora - A very efficient low-latency protocol that uses the least possible amount of logic while offering excellent performance. • We’ll use this core for the Internal Network (FSB).

  18. Block Diagram High Speed Digital Systems Lab Virtex 6 ML605 Evaluation Board Micro Blaze ExternalNetwork FSB Internal Network SMA Connectors Tx FIFO RJ45 Connector Tri-Mode Embedded Ethernet MAC Protocol Translator TCP/IP - Ethernet Aurora IP Core GTX Transceiver lwIP Rx FIFO Ethernet Aurora Protocol

  19. The Protocol Translator High Speed Digital Systems Lab The protocol translator will be implemented in Xilinx SDK and will be written in C++. This unit will translate packets from Aurora protocol to TCP/IP and vice versa.

  20. Progress so far High Speed Digital Systems Lab • Acquiring extended knowledge of: • Virtex 6 ML605 FPGA. • ISE 11.5/12.1 and its tools (SDK, LogiCore Generator, XPS) • In depth self-study of Ethernet & TCP/IP protocols. • Creating Basic Microblaze & testing it on the board. • Designing the platform’s block diagram.

  21. Detailed Time Line (Sem. A) High Speed Digital Systems Lab

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