High Speed Testing of the Aeroflex RadHard Eclipse FPGA

1. High Speed Testing of the Aeroflex RadHard Eclipse FPGA Craig Hafer Melanie Berg Roger Kim Hak Kim Ray Ladbury Aeroflex Colorado Springs NASA Goddard Space Flight Center Colorado Springs, CO 80907 Greenbelt, MD 20771 Craig.Hafer@Aeroflex.com www.Aeroflex.com/RadHard

2. Outline • Device Status • Device Description • Previous SEE Performance • High Speed SEU Performance • Summary/Conclusions

3. Device Status • QML Q qualified August 2005 • QML product shipped September 2005 • QML V qualification work on-going • SEL immune to greater than 120 MeV-cm2/mg • TID hardened to greater than 300 krad(Si) • SEU hardened – Results presented

4. Device Description • FPGA with one time programmable ViaLinkTM • 2.5 V Core and 3.3V I/O power supplies • 55,296 hardened bits of SRAM • 3072 hardened flip-flops • 930 hardened I/O flip-flops • Built on 0.25mm EPI CMOS technology

5. SEL Immune • Greater than 120 MeV-cm2/mg • Fluence up to 1 x 108 ions/cm2 • 125°C • Maximum VDD (3.6V I/O, 2.7V core) • Texas A&M University • Au ion (15 MeV/amu)

6. Previously Reported SEU Data – 1 MHz 1024 bit (64 x 16) Register file 4.4 x 10-9 errors/bit-day

7. Previously Reported SEU Data – 1 MHz 1120 stage (two at 560) shift register 2.2 x 10-8 errors/bit-day

8. Previously Reported SEU Data – 1 MHz 55,296 bit RAM 6.9 x 10-10 errors/bit-day

9. Previously Reported Proton Data – 1 MHz

10. Previously Reported Proton Data

11. High Speed Testing Procedure • SEU testing targets speeds up to 120 MHZ • Purpose is to investigate SEU frequency and architectural dependencies • Shift registers – 140 or 1120 stages • Fanout – enable through 8 inverters to four flip-flops • Combinatorial logic between shift register stages – 0 or 8 inverters

12. Test Setup

13. Device Under Test

14. 140 or 1120 DFF’s 140 or 1120 DFF’s 8F8L: 140 DFF’s N=8 with fanout 8F0L: 140 DFF’s N=0 with fanout 0F8L: 140 DFF’s N=8 no fanout 0F0L: 140 DFF’s N=0 no fanout Q1120: 1120 DFF’s N=0 no fanout Shift Register Configuration

15. High Speed SEU Cross-section vs LET

16. High Speed SEU Cross-section vs Frequency

17. High Speed SEU – Cross section vs Frequency by Data Type (LET = 21)

18. High Speed SEU – Cross section vs Frequency by Data Type (LET = 54)

19. Shift Register Configuration Effects Xe LET = 56 Xe LET = 79

20. 120 MHz Proton Results • Five runs each of 8F8L, 8F0L, and Q1120 configurations • 1 x 1012 protons/cm2 fluence (300krad(Si) per device) • Q1120 device had 1 upset

21. Summary/Conclusions • Previous low frequency SEE data reviewed • SEL immune to greater than 120 MeV-cm2/mg • Bit cross-section insensitive to frequency • 12 MHz to 100 MHz • Alternating ones and zeros is worst case with respect to bit cross-section • Combinatorial logic and fanout did not increase the error cross-section