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Optimizing CMOS Switch Design for R-2R Voltage DAC Performance Enhancements

This presentation discusses CMOS switch design and simulation techniques for improving R-2R Voltage DAC performance. It covers challenges such as virtual ground adjustment, glitch reduction, and resistor implementation in layouts. Advantages and disadvantages of Voltage R-2R DAC are explored, along with testing methodologies and linear output characterization. Key topics include op-amp design, frequency response analysis, and output buffer characteristics.

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Optimizing CMOS Switch Design for R-2R Voltage DAC Performance Enhancements

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  1. Design of Digital-to-Analog Converter EE597G Presentation: Qin Chen Yong Wang Dept. of Electrical Engineering Mar. 14th, 2006

  2. Outline • CMOS switch design and simulation • Challenge and Solution • R-2R Voltage DAC • Schematic design and simulation results Chip Specifications • Project Progress

  3. CMOS Switch Circuit

  4. Turn on resistance Control signal is high: • When Vin<Vdd-Vgs1, M1 is turned on; • When Vgs2<Vin<Vdd, M2 is turned on; • The total parallel resistance make the turn-on resistance always low at the whole voltage range.

  5. Simulation Results VG=+5V, RL=10k Ohm VG=0V, RL=10k Ohm

  6. Challenge • For R-2R current DAC, how to change virtual ground to 2.5V in CMOS circuits? • How to get rid of glitches? • How to implement large resistors (>10k ohm) in layout? [next step]

  7. Glitches in DAC output voltages • Switches in DAC operate at different speeds ⇒ output glitches occur when several input bits change together: 0111->1000 • Glitches are very noticeable on a video display:

  8. Voltage-Mode R-2R Network DAC

  9. Advantages and Disadvantages of Voltage R-2R DAC Advantages: • the constant output impedance, which eases the stabilization of any amplifier connected to the output node. • No glitch, switch the arms of the ladder between low impedances, capacitive glitch currents tend not to flow in the load. Disadvantages: • operate over a wide voltage range (VREF to GND). This is difficult from a design and manufacturing viewpoint • gain of the DAC cannot be adjusted by means of a resistor in series with the VREF terminal.

  10. D9-D0: 10,0000,0000 Vref: +5V

  11. Linear output characterization

  12. Testing the op amp

  13. Freq. Response of Gain & Phase

  14. Compensation

  15. Compensation result

  16. Output buffer

  17. The output curve of output buffer

  18. Voltage Reference

  19. ─ + Characteristics of voltage reference 5V 5V 20K Rload Vout=2.5V 20K

  20. Building the DAC

  21. Test the DAC

  22. Test result of DAC

  23. What have been done • OP Amp design and simulation • CMOS switch design and simulation • Schematic adjustment • Schematic circuit design and simulation

  24. Project Progress =>>

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