TDAQ news and issues

1. TDAQ news and issues M. Sozzi NA62 TDAQ WG meetingCERN – 20/10/2010

2. Outline • TEL62 • TDCB • Clock • L0 processor • Interfacing to PCs • Simulation

3. TEL62 - overview Newer FPGAs and memories Doubled bus bandwidth with SL-FPGA Fewer I/O pins in new chosen PP-FPGA +constraints for compatibility with LHCb cards = After price confirmation for 500 FPGAs:increased size of PP-FPGA. All 5 FPGAs on the TEL62 of the same type:EP3SL110F1152C4N (4x the original) Additional pins used for communication bus between PP-FPGAs (useful for LKr/L0) Internal note NA62-10-06 distributedComments from Lausanne group received

4. TELL1 PP PP GbE SL PP PP

5. TEL62 PP PP GbE SL PP PP

6. TEL62 - status Some trouble with power distributionDifficult to estimate power consumption before firmware is ready Design finished and start layout work at CERN at beginning of November Components for 2 prototypes being procured Production tests, firmware development, etc. ?

7. TDCB – status and plans Some delays in mounting2 prototypes of V4 expected next week Firmware debugging ongoing Detailed documentation being written Need to prepare test-bench system Preliminary tests in Pisa Collect orders for first batch First batch production (<16): [these might be used in a synchronization run] Tests and validation by sub-detector groups

8. TDCB – validation

9. Components Please check and update!

10. Clock - modules 2 NA62 LTU prototypes available, ready for testing at CERN (Birmingham)Then: full production (19+ modules), paid 19 new TTCex modules for NA62 in production Need to finalize number of lasers: Birmingham will distribute a final poll Payment to NA62 account 5 old TTCex available in E-POOL

11. Clock - infrastructure NA48 clock generator seems OK (spare?) Organize central purchase of splitters, attenuators, fibres (Birmingham) Finalize “officially supported” VME CPU Install central crate(s) + CPU Sub-detectors: define TTC distribution network Lay down fibres in ECN3

12. Burst sequence Start of burst signal (via TTC special command):reset timestamp counters Start of burst trigger (via TTC):can send data Normal triggers…send data End of burst signal (via TTC special command):store timestamp counter value End of burst trigger (via TTC):send end-of-burst data, stop data-taking Sub-detectors only see 2 hardware signals: START OF BURST and END OF BURST

13. Calibration triggers Sub-detector drives sub-detector calibration system and sends signal pulse to L0TP L0TP delivers (if possible, if allowed) calibration trigger (after fixed, small delay) In-burst vs. Out-of-burst calibrations:L0TP knows when the beam really ends (EE), and can:- Deliver special control trigger (e.g. to instruct sub-detectors to change pulser parameters)- Modify acceptance rules for calibration triggers This scheme avoids need for additional trigger and synchronization lines

14. Central (L0) Trigger System(logical) Pulser 40MHz Gen CHOD Time-match L0 primitives,decide L0 and trigger type, check latency, downscale, monitor Record L0 data MUV Data (GbE) Farm LKR/L0 L0 primitives (GbE) Burst SPS LAV (RICH) Burst (GbE) Farm Generate special triggers Monitor & recordchoke/error,send special triggers Re-sync, encode Clock, L0, Burst (TTC) All sub-detectors Choke/Error (LVDS) All sub-detectors

15. Central (L0) Trigger System(functional) Pulser 40MHz Gen CHOD MUV Data (GbE) Farm LKR/L0 L0 primitives (GbE) Custom FPGA-basedboard OR Real-time capablePC PC interface Burst SPS LAV (RICH) Burst (GbE) PC (DIM) Farm Spare Re-synchronizer Clock, L0, Burst (TTC) All sub-detectors Choke/Error (LVDS) TTC modules All sub-detectors

16. Central (L0) Trigger System(implementation) Pulser 40MHz Gen Fan-out CHOD MUV Data (GbE) Farm GbE TX LKR/L0 L0 primitives (GbE) GbE RX Burst SPS LAV Burst Fan-out (RICH) Burst (GbE) PC (DIM) Farm Spare PCIe Corelogic PCIe L0 Fan-out LTU TTCex Clock, L0, Burst (TTC) All sub-detectors Choke/Error (LVDS) All sub-detectors Re-syncmemory PCIe custom board Custom board or PC

17. L0TP: Real-time tests (Ferrara) CPU Involvement of very experienced group working on APE. Using a custom board with 2 Intel CPUs (standard Linux, so far) and FPGAs to test real-time response of a basic L0TP algorithm PCI-express FPGA

18. L0TP: Real-time tests (Ferrara) First naïve results: latency FPGA → CPU → MEM → FPGAwith 0 computation timeand standard Linux(depending on output buffering) Now making more tests with more realistic time-matching algorithm 11μs 18μs 25μs Further tests using standard PC and Pisa Altera Stratix IV PCIe development board (can such system be a L0TP?) Expect report at next meeting

19. L0 Trigger Processor Rather limited progress Detailed descriptive note in preparation Temporary solution might be quite different from final system

20. Interfacing to PCs Started development in Pisa of buffer managercode for readout User-space independent processes Fixed-format shared memory GbE GbE GbE GbE Sharedmemory CONS PROD CONS PROD CTRL CONS PROD CONS PROD Procs

21. To be used for: L1 PCs Multiple processes either running L1 (single sub-detector) algorithm or reading sub-detector data to L2 farm(on different event sets) GbE GbE Sub-detector data L1 algo L1primitives L1 algo L1 Trigger Processor PC L1 algo Sub-detector data L2 farm Readout

22. Maybe also: software L0 ? Multiple GPUs running L0 primitive generation (for some sub-detector). Algorithm time and latency not an issue. Raw data-transfer time not an issue. Control time? From CPU thread without operating system?From hardware PCIe sequencer? GbE CondensedSub-detector data GPU L0primitives GPU L0 Trigger Processor GPU GPU

23. Online software / run control • Existing solutions (DIM, SMI++) seem adequate • Possible help from CERN DCS group to port some of the above solutions to NA62 • Need coordination and expertise within NA62 • Write note describing NA62 requirements (volunteers willing to help?)

24. Towards a run control Common interface to run control: Single machine per sub-system Respond to the following commands:- Enable/disable global control- Cold-start initialization- Start run <number> <global_conf> <local_conf>- End run- Query status- Reset No need of start/end burst (special triggers)

25. Simulation - Tools Some work started (see talks). - Do we have everything we need for trigger simulation in the official MC?Can it be ran in a fast enough mode? - Do we need a fast parameterized MC?

26. Simulation - Issues - Verification of L0 rates- How much below 1 MHz can we stay?- Effect of LAV? - Which control triggers can be allowed? - CHOD/RICH vs. MUV acceptance matching - Can CHOD be used in L0? Efficiency (accidentals)?- How much can RICH add? (At L1?) - How much can STRAWS contribute at L1? - What can be done realistically with LKr tiles at L0? Can something more be done with tiles at L1? Is some (summary) single-cell information useful at L1? - Most significant correlation cut at L2?Which sub-detectors are required at L2?With which resolution?

27. Synchronization run? TEL62 test and firmware No help available within NA62- Roma Tor Vergata cannot help in common TEL62 firmware development- Still missing sub-detector involvement in firmware Possibility of help from a PhD student in the STRAWS group L0 Trigger Processor Need commitments and tests