Design, Synthesis and Test of Network on Chips

1. University of Tehran Technical faculty Electrical and Computer Engineering Faculty Design, Synthesis and Test of Network on Chips Presented By: Atefe Dalirsani ASIC Course Instructor: Dr. S. M. Fakhraei May 2006 Class Presentation for Educational Purposes

2. Outline • On-chip bus architecture problem • NoC design • NoC design trade-offs and considerations • Switch block design • Performance evaluation • NoC synthesis • NoC synthesis tools • Testing NoC based systems • Reliable SoC/NoC Design

3. On-chip Bus Architecture Problems • 2010: MPSoC devices, many GHz, below one volt, complex communication architectures • In today’s SoC devices, all of the IP blocks are connected by global on-chip buses but this global interconnect is increasingly dominating the delay, power, and area of integrated circuits • Traditional on-chip bus architectures are becoming a bottleneck for two reasons:[4] • bus interface in each IP block needs to be frequently modified • interconnections in each new technology generation, become more complex as they need to connect more on-chip functions with the result that cost/performance factors such as silicon area, on-chip communications speed and overall power consumption are increasingly dominated by the bus.

4. NoC Solution • NoC is a new concept that emerged from the academic world as recently as 2000 and has since been the subject of intensive academic and industrial research. Numerous innovative NoC architectures have been proposed by a variety of universities and industrial research labs, including KAIST (Korea Advanced Institute of Science and Technology), KTH (Royal Institute of Technology, Sweden), Laboratoire d’Informatique de Paris 6, MIT, Philips Research Lab, STMicroelectronics, Technion (Israel Institute of Technology), and VTT Technical Research Centre (Finland), as well as Universities such as Bologna, Manchester, San Diego, Stanford, and Tampere. • Many issues about NoC concepts as a solution for MPSoC interconnects are still open such as: the choice of the network topology, the packet and message format, the end-to-end services, the routing strategies, the flow control and the queuing management • The user expects answers in the tens of topics involved in 'real world' NoC design such as: reset, QoS, testability, application debug, timing convergence, error logging, compatibility with existing standard, etc.[3]

5. [1] NoC Design • Network-on-a-chip (NoC) paradigm is emerging as a new design methodology to meet the communication requirements of large SoCs  new trends • Various trade-offs regarding latency, throughput, reliability, energy dissipation, silicon area requirements and application’s nature characterize communication-centric interconnect fabrics • Borrow communication models and techniques from networking and parallel processing  micronetwork  energy efficiency and QoS

6. [2] Design Trade-offs for NoCs • Throughput: the maximum load the network can physically handle  system aggregate bandwidth • Latency: the time that elapses between a message injection into the network at the source node and the end of packet reception at the destination node. • When data travels on the interconnection network, both the inter-switch wires and the logic gates in the switches toggle.  energy dissipation • Additional buffer and register area, estimating wire area complexity  longest wire segments,

7. Design Considerations • Performance perspective: high throughput and low latency (such as MPSoC platforms) • VLSI perspective: interconnect architecture’s energy dissipation profile significant portion of the overall energy budget • Silicon area overhead resulting from the interconnect fabric • Processor and storage cores communicate with one another through high-performance links and intelligent switches, and communication design can be represented at a high abstraction level.

8. Switch Block Design • Packet-based on-chip communication • Wormhole switching • Divide packets into fixed-length flow control units (flits) • I/O buffers for storing only a few flits • Minimizes the buffer space in the switches  switches are small and compact • Header flit decoding enables switches to establish the path • Subsequent flits simply follow this path in a pipeline fashion • If a flit faces a busy channel, subsequent flits must wait at their current locations

9. [1] Switch Bock Design (Cont.) • Routing scheme • Deterministic • Adaptive

10. Performance Evaluation • NoC-based interconnect performance correlates strongly with the topology  regular , irregular • Regular arch. : performance level is homogeneous across the whole system  for the realization of multiprocessor communication schemes • Irregular arch. : vary widely for the different processors and storage blocks  for realizing application specific SoCs such as those in mobile-phone systems

11. NoC Synthesis • NoCs have no specialized languages or formalisms for their high-level modeling • Synthesis is useful in both homogeneous and heterogeneous network architectures. • Designers can realize the network by means of components such as switches, links, and network interfaces.

12. Reasons for Using NoC synthesis • Sometimes the best network architecture, protocols, and parameters for a given system application aren’t known. • There are many parameters to optimize in an on-chip network implementation. • A synthesis flow allows fast design and lets designers concentrate on system issues while leaving details to the tools

13. NoC Synthesis Tools • NoC libraries : xPipes, xPipesLite [1] • xPipes Compiler: a network synthesis tool for xPipes [1] • Sunmap9: automatic topology selection tool [1] • Arteris: develops and markets products enabling chip designers and system architects to effectively build the on-chip communications infrastructure for chips comprised of many discrete building blocks [3]

14. [1] xPipes Compiler

15. Arteris NoC Solution [3]

16. Sunmap – Automatic Topology Selection Tool [1]

17. Testing NoC-based Systems • Testing functional and storage blocks and their corresponding network interfaces • Several parallel path for transmitting test data • Testing the interconnect infrastructure • Testing the switch blocks • FIFO buffer • Router logic • Testing the inter-switch wire segments • Testing the integrated system

18. Reliable SoC/NoC Design • Error control coding • Advantage of packetized communication is the possibly of incorporating error-control information into the transmitted data stream • Distributed error recovery mechanism • Centralized error recovery mechanism • Fault tolerant architectures

19. Conclusion • Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single SoC • Several industrial and academic research groups are striving to develop efficient communication architectures • NoC is an enabling solution for this level of integration • Major issues include the detailed design trade-offs and the performance optimization • NoC tools for design and synthesis in higher levels of abstraction

20. References [1]: P. P. Pande et al., “Design, Synthesis and Test of Networks on chips,” IEEE design & test of computers, Sep. 2005. [2]: P.P. Pande et al., “Performance Evaluation and Design Trade-offs for Network-on-Chip Interconnect Architectures,” IEEE Trans. Computers, vol. 54, no. 8, Aug. 2005, pp. 1025-1040. [3]: www.arteris.com [4]: www.soccentral.com [5]: S. Kumar et al., “A Network on Chip Architecture and Design Methodology,” IEEE computer society annual symposium on VLSI, 2002 [6]: M.Hosseinabady et al, “A Concurrent Testing Method for NoC Switches,” DATE Conference, 2006.