A new FEEB & ROCB Design issues for the next stage DAQ Chain for MUCH

1. A new FEEB & ROCB Design issues for the next stage DAQ Chain for MUCH Madhusudan Dey VECC,KOLKATA CBM collaboration meet at VECC 30th July – 1st August, 2010

2. ABB ROC FEEB DCB DET BNeT FLES ABB Legacy DAQ Chain FEEB ROC: Readout Controller Board

3. Data Combiner:Data Reduction FPGA Brd.TX/RX Annex Building Optical Link Optical Link 60 meter 300 meter Dipole magnet, Silicon Tracking Stations and Muon detection system Requirements for GEM PCBS: Station:1 135 ×135 sq mm for 281 Modules cater·287,500 Readout Channels FEEBa2! Size of the Board Important! Station:2 + Station:3 · 326.2×326.2 sq mm for 228 Modules Caters 232,500 Readout Channels FEEBa4! Size of the Board Important! Main Computing Building SIS-100 geometry

4. (left) modular type arrangement and (right) slat type arrangement of modules The options, other than the module-type will need GEM foils of non-standard sizes and we need to find suitable vendor for doing this. We have however kept the options open so that we can take a final call at suitable time. Sector type layout of the stations Detector PCB

5. Communication HUB • A radiation tolerant ASIC HUB Chip for data aggregation & communication , capable of aggregating data from several Front end Asics (FEEB) onto a single output link • Data from 2, 4 or 8 CBM-XYTER chips (FEBa2, FEBa4 and FEBa8, respectively) can be aggregated to fill a 2.5 Gbps link based on a 2.5 Gbps SERDES circuit. • The ‘Hub Asic’ must also be able to handle clock distribution, sync and slow control traffic and operate with a deterministic latency at the Word clock level. • Convert the input data from FEEB into a serial stream (Cu or Optical?) • De-serialize the frame transmitted from the computing building and feed the data to the FEEB.

6. PCB front view ……………………………. Pads Optical link ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC M U X M U X M U X M U X PCB back view ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC M U X M U X M U X M U X M U X ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC PCB Board with Optical HUB ASIC ASIC Many such FEE PCBs & HUBs inside the MUCH FEBa8 FEBa4 Each ASIC supports 128 channels..

7. VIRTEX 6 FPGA BOARD • Capable of handling 6.6 Gbps Links(12-48) • Capable of handling few 11.18 Gbps Links Links (24 nos) • Can be implemented data reduction algorithm based on certain predefined fixed criteria • Have enough space for other collaborators try their own algorithm • Design & fabrication feasible • Prototype board developments require 6-9 months • Can suggest procedures for board functionality tests • Can suggest form factors and nos. • Can suggest communication protocol w.r.t HUB • At most handle 48 links equivalent to minimum of 48 X256 =12288 CHANNELS new ROCB WITH DATA REDUCTION = 42 nos. 2.5 Gbps from HUB 2.5 Gbps from HUB

8. VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD VIRTEX 6 FPGA BOARD 12 CH O P T I C A L TX/RX 24 Links per board possible ROCB nos reduce to 42 nos for 5.2 lakh channels Conceptual Schema for ANNEXE Building

9. 8 Questions??? • 4x4 mm pads ? • Hit rate 2.5 MHz per channel • FEBa2 ? FEBa4 ? FEBa8 ? • Gross data rate? • SLAT TYPE ? • Form Factor FEEB /LAYOUT /Wiring Details ? • HUB Board Design & Fabrication( Who & When?) • Multi channel Trans/Receiver 10 Gbps available with 12 channel ?