Lecture 22: Multistage Amps

1. Lecture 22:Multistage Amps Prof. Niknejad

2. Lecture Outline • Finish Current Mirrors • An Example Using Cascodes • Multistage Amps • Cascode Amplifier: Magic! University of California, Berkeley

3. The Integrated “Current Mirror” • M1 and M2 have the same VGS • If we neglect CLM (λ=0), then the drain currents are equal • Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1 • We say that the current IREF is mirrored into iOUT • Notice that the mirror works for small and large signals! High Res Low Resis University of California, Berkeley

4. Current Mirror as Current Source • The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET • M2 acts like a current source to the rest of the circuit University of California, Berkeley

5. Small-Signal Resistance of I-Source University of California, Berkeley

6. Improved Current Sources Goal: increase roc Approach: look at amplifier output resistance results … to see topologies that boost resistance Looks like the output impedance of a common-source amplifier with source degeneration University of California, Berkeley

7. Effect of Source Degeneration • Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance • Output impedance is boosted by factor University of California, Berkeley

8. Cascode (or Stacked) Current Source Insight: VGS2 = constant AND VDS2 = constant Small-Signal Resistance roc: University of California, Berkeley

9. Drawback of Cascode I-Source Minimum output voltage to keep both transistors in saturation: University of California, Berkeley

10. Current Sinks and Sources Sink: output current goes to ground Source: output current comes from voltage supply University of California, Berkeley

11. Current Mirrors Idea: we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier. University of California, Berkeley

12. Multistage Amplifiers • Necessary to meet typical specifications for any of the 4 types • We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and the npn versions of CE, CB, and CC (for a BiCMOS process) • What are the constraints? • Input/output resistance matching • DC coupling (no passive elements to block the signal) University of California, Berkeley

13. Summary of Cascaded Amplifiers • General goals: • Boost the gain parameter (except for buffers) • Optimize the input and output resistances University of California, Berkeley

14. CE2 CE1 Start: Two-Stage Voltage Amplifier • Use two-port models to explore whether the combination “works” CE1,2 Results of new 2-port: Rin= Rin1,Rout= Rout2 University of California, Berkeley

15. Add a Third Stage: CC Goal: reduce the output resistance (important spec. for a voltage amp) CE2 CC3 CE1 Output resistance: University of California, Berkeley

16. Using CMOS Stages CS2 CD3 CS1 Input resistance: Voltage gain (2-port parameter): Output resistance: University of California, Berkeley

17. Multistage Current Buffers Are two cascaded common-base stages better than one? Input resistance: Rin = Rin1 University of California, Berkeley

18. Two-Port Models Output impedance of stage #1 (large) University of California, Berkeley

19. Common-Gate 2nd Stage University of California, Berkeley

20. Second Design Issue: DC Coupling Constraint: large inductors and capacitors are not available Output of one stage is directly connected to the input of the next stage  must consider DC levels … why? 3.2V University of California, Berkeley

21. Alternative CG-CC Cascade Use a PMOS CD Stage: DC level shifts upward 3.2V University of California, Berkeley

22. CG Cascade: DC Biasing Two stages can have different supply currents Extreme case: IBIAS2 = 0 A University of California, Berkeley

23. CG Cascade: Sharing a Supply First stage has no currentsupply of its own  its outputresistance is modified University of California, Berkeley

24. The Cascode Configuration Common source / common gatecascade is one version of a cascode (all have shared supplies) DC bias: Two-port model: first stage has no current supply of its own University of California, Berkeley

25. Cascode Two-Port Model Output resistance of first stage = Why is the cascode such an important configuration? University of California, Berkeley

26. Miller Capacitance of Input Stage Find the Miller capacitance for Cgd1 Input resistance to common-gatesecond stage is low  gain acrossCgd1 is small. University of California, Berkeley

27. Two-Port Model with Capacitors Miller capacitance: University of California, Berkeley

28. Generating Multiple DC Voltages Stack-up diode-connected MOSFETs or BJTs and run a reference current through them  pick off voltages from gates or bases as references University of California, Berkeley

29. Multistage Amplifier Design Examples Start with basic two-stage transconductance amplifier: Why do this combination? University of California, Berkeley

30. Two-Stage Amplifier Topology Direct DC connection: use NMOS then PMOS University of California, Berkeley

31. Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for iSUP 2 University of California, Berkeley

32. Use Basic Current Supplies University of California, Berkeley

33. Complete Amplifier Topology What’s missing? The device dimensions and the bias voltage and reference resistor University of California, Berkeley