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Yu Bai and R. Iris Bahar Brown University Division of Engineering

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. Yu Bai and R. Iris Bahar Brown University Division of Engineering. Motivation. Performance and power trends Many complex architectural features are included

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Yu Bai and R. Iris Bahar Brown University Division of Engineering

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  1. A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors Yu Bai and R. Iris Bahar Brown University Division of Engineering

  2. Motivation • Performance and power trends • Many complex architectural features are included • These features consume power regardless of usage • Adjustable datapath resources to match the application’s needs • Focus on issue logic consume a large portion of the overall power ISVLSI 2003

  3. Our Approach • FIFO-structured issue queue • Dependent instructions are inserted into one FIFO • Instructions are issued from FIFOs in parallel • In-order & out-of-order issuing combining • Only the instruction at the head of each FIFO is visible to the request and selection logic ISVLSI 2003

  4. 30% drop 84% drop Fixed-Sized FIFOs ISVLSI 2003

  5. Reorder Buffer Branch Prediction Unit Hardware Performance Monitors & Controls Register Rename Unit Fetch Unit Commit Unit Register File Functional Units Instruction cache Data Cache Pipeline Organization 6 64-entry Issue Queue (FIFOs) 6 6 ISVLSI 2003

  6. req 3 gnt 3 req 4 gnt 4 Issue Queue Scheme 1: variable number of FIFOs req 1 gnt 1 FIFO 1 req 2 Selection Logic gnt 2 4 instructions bid for the issue slot FIFO 2 FIFO 3 FIFO 4 4 Active 2-entry FIFOs (FPM) ISVLSI 2003

  7. req 3 gnt 3 Issue Queue Scheme 1: variable number of FIFOs req 1 gnt 1 FIFO 1 3 instructions bid for the issue slot req 2 Selection Logic gnt 2 FIFO 2 FIFO 3 FIFO 4 3 Active 2-entry FIFOs (LPM1) ISVLSI 2003

  8. Issue Queue Scheme 1: variable number of FIFOs req 1 gnt 1 2 instructions bid for the issue slot FIFO 1 req 2 Selection Logic gnt 2 FIFO 2 FIFO 3 FIFO 4 2 Active 2-entry FIFOs (LPM2) ISVLSI 2003

  9. req 3 gnt 3 Issue Queue Scheme 1: variable number of FIFOs req 1 gnt 1 FIFO 1 3 instructions bid for the issue slot req 2 Selection Logic gnt 2 FIFO 2 FIFO 3 FIFO 4 3 Active 2-entry FIFOs (LPM1) ISVLSI 2003

  10. req 3 gnt 3 req 4 gnt 4 Issue Queue Scheme 1: variable number of FIFOs req 1 gnt 1 FIFO 1 req 2 Selection Logic gnt 2 4 instructions bid for the issue slot FIFO 2 FIFO 3 FIFO 4 4 Active 2-entry FIFOs (FPM) ISVLSI 2003

  11. FIFO 1 FIFO 8 FIFO 2 FIFO 3 req 1 req 2 req 3 req 8 gnt 3 gnt 1 gnt 2 gnt 8 Issue Queue Scheme 2: variable sized FIFOs Selection Logic 8 instructions bid for the issue slot 8 1-entry FIFOs (FPM) ISVLSI 2003

  12. req 1 req 2 req 3 req 4 FIFO 1 gnt 2 gnt 3 gnt 1 gnt 4 FIFO 2 FIFO 3 FIFO 4 Issue Queue Scheme 2: variable sized FIFOs Selection Logic 4 instructions bid for the issue slot 4 2-entry FIFOs (LPM1) ISVLSI 2003

  13. req 2 req 1 gnt 2 gnt 1 FIFO 1 FIFO 2 Issue Queue Scheme 2: variable sized FIFOs Selection Logic 2 instructions bid for the issue slot 2 4-entry FIFOs (LPM2) ISVLSI 2003

  14. req 1 req 2 req 3 req 4 FIFO 1 gnt 2 gnt 3 gnt 1 gnt 4 FIFO 2 FIFO 3 FIFO 4 Issue Queue Scheme 2: variable sized FIFOs Selection Logic 4 instructions bid for the issue slot 4 2-entry FIFOs (LPM1) ISVLSI 2003

  15. FIFO 1 FIFO 8 FIFO 2 FIFO 3 req 1 req 2 req 3 req 8 gnt 3 gnt 1 gnt 2 gnt 8 Issue Queue Scheme 2: variable sized FIFOs Selection Logic 8 instructions bid for the issue slot 8 1-entry FIFOs (FPM) ISVLSI 2003

  16. Hardware Performance Monitors • Issue IPC • IPC variations • Performance degradation • Ready instructions • Issue queue occupancy • Non-critical instructions ISVLSI 2003

  17. Issue Queue Power Breakdown • Components of issue logic • Register files • Register mapping • Issue queue (50% of issue logic power) ISVLSI 2003

  18. Pchg_clk Request Logic (taken from 21264) clk cond Req_H Req_L state_cond EX_cond reg1_rdy reg0_rdy ISVLSI 2003

  19. FIFO_head Pchg_clk Request Logic (taken from 21264) clk cond Req_H Req_L state_cond EX_cond reg1_rdy reg0_rdy ISVLSI 2003

  20. Issue Queue Scheme 1 ISVLSI 2003

  21. Issue Queue Scheme 1 >75% 64% 4.7% 3.6% ISVLSI 2003

  22. 70% of the time only 2-4 FIFOs needed Issue Queue Scheme 2 ISVLSI 2003

  23. Issue Queue Scheme 2 ISVLSI 2003

  24. Issue Queue Scheme 2 ISVLSI 2003

  25. Issue Queue Scheme 2: fpppp 11.8% ISVLSI 2003

  26. Conclusion • Dynamically reconfigurable, FIFO-structured issue queue can save power with negligible performance impact • Scheme 1: fixed sized FIFOs save more power but not as flexible • Scheme 2: variable sized FIFOs offer good compromise (27% issue queue power savings) • Future work to combine this scheme with orthogonal techniques ISVLSI 2003

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