Linac 4 LL RF Hardware Architecture and Design Status

1. Linac 4 LL RF Hardware Architecture and Design Status • Gregoire Hagmann, Jose Noirjean, DonatStellfeld, Daniel Valuch, JulienLollierou, Anirban Krishna Bhattacharyya, Philippe Baudrenghien • CERN-BE-RF-FB • John C. Molendijk CERN-BE-RF-CS Reported by John C. Molendijk CERN-BE-RF-CS J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

2. Outline • Linac 4 LL RF hardware Architecture and Design Status • Hardware Architecture • Block Diagram • Chassis • Linac 4 Clocking Scheme • Cavity Loops Module • Switch & Limit Module • Tuner Loop Module • Conditioning DDS • Status of Electronic Designs J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

3. Linac 4 LL RF Block Diagram J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

4. Linac 4 LL RF Chassis • Private backplane (Based on LHC LL RF system) • Low noise Analog power supplies. • Fully buffered, Quad low-jitter differential clock distribution. • Hardware Timing distribution for chopping information etc. • Serial distribution of Reference RF phase. • 220 mm deep slots offering sufficient real-estate for RF circuitry. • Geographical VME addressing. • Crate-wide JTAG enabling remote FPGA flashing through the crate manager module. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

5. Linac 4 LL RF Chassis Occupation J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

6. Linac 4 LL RF Chassis J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

7. Linac 4 ClockingScheme • A RF reference-line will propagate the 352 MHz reference RF all along Linac4 • At each cavity a directional coupler will extract some of the reference RF from the reference-line. • The antenna signals are routed in a bundle with the reference RF towards the cavity controller crate. All signals are submitted to similar drift effects. • At the cavity controller the reference RF is used to normalize the Antenna RF signal phase making these acquisitions robust against phase drift incurred by the cabling. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

8. Linac 4 ClockingScheme IQ Sampling & ADC Offset Compensation TADClk • Clocks Required for RF LL • Reference RF. • Local Oscillator (LO) for the mixers (Receivers and Modulators). • ADC clock (4 * fIF). • ADC clock /2 and ADC clock /4 for IQ demodulation. • 10 MHz reference clock. • Critical Clocks • Reference RF, LO and ADC clock must have very low phase noise (jitter) to minimize demodulation errors and to maintain the effective number of bits (ENOB) in the Digital RF Receivers. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

9. Linac 4 Clocking Scheme • LHC case • The beam synchronous RF is generated in SR4 (surface building) and then optically transported to the UX45 (cavern) faraday cages. • All RF synchronous clocks are there derived from the SR4 reference by one central clock Generator per beam. • A distribution system supplies the reference RF and all generated clocks (380, 80, 40 and 20 MHz) to all 8 cavity controllers crates per beam. • Linac 4 • Reference RF is generated from a high quality Oscillator which is then amplified (~100W) to drive the Linac 4 RF reference line. • All RF synchronous clocks are derived and distributed within each cavity controller. Big savings in distribution and improved clock signal quality. • The Locally generated and distributed LO does not have to be phase drift stabilized since both the down and up convertors use the same (see p13). • The cavity controller’s Clock Generator Distributors receive and demodulate the Reference RF. The measured phase is distributed serially over the backplane to allow all modules to normalize their acquisitions. No need for individual ref. RF receivers per module. • Only the absolute 10 MHz reference is distributed individually. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

10. Linac 4 Clocking Scheme Clock Generator Distributor per Cavity Controller J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

11. Linac 4 Clocking Scheme Phase Discriminator J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

12. Linac 4 Clocking Scheme ADF4106 R =16 N =15 Using std VCO Using Coaxial resonator based VCO LO L4 Jitter = 270 fs, Band integrated [10Hz-10MHz] Retained solution LO L4 Jitter= 120 fs LO LHC Jitter=264 fs J.C. Molendijk - Linac 4 Hardware Architecture and Design Status New Low noise LO PLL and distribution Designer J. Lollierou

13. Cavity Loops Module System Independent of LO phase Implements: RF Feedback, Adaptive FF and Klystron Polar Loop IQ Demodulators synchronized by Fc(use same demux signals as Ref-line demodulator). De-serialized Reference-line RF Phase used to normalize the phase of the RF Measurements. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

14. Linac 4 Switch and Limit Avoids overdriving the Klystron Pin Pdrive Designer G. Hagmann Block Diagram J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

15. Linac 4 Tuner Loop Front-end Designer J. Noirjean Simplified Block Diagram J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

16. Linac 4 Tuner Loop Front-end Designer J. Noirjean J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

17. Linac 4 Tuner Loop Module Common for all Linac4 structures: DSP or Software customized, L. Arnaudon E_IcFwd = Vcav X IcFwd VME register Optimal Vcav Phase Designer J. Noirjean Simplified Block Diagram J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

18. Linac 4 Conditioning DDS Prototype to be tested on DTL prototype, end 2010 DDS IF ~48 MHz Simplified Block Diagram J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

19. Status of Electronic Designs Modules J.C. Molendijk - Linac 4 Hardware Architecture and Design Status

20. Thank you for your attention. J.C. Molendijk - Linac 4 Hardware Architecture and Design Status