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This section explores the design and operation of NMOS transistors in digital integrated circuits, focusing on a simple switching circuit with variable threshold voltage. Topics covered include determining the region of operation, selecting drain terminal, calculating parameters such as Kn and Vth, and analyzing noise margin and signal amplification. Examples and simulations are used to illustrate concepts.
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Applications of MOS Transistors in Digital Integrated Circuits (1) Section 15.1
ADD an Instance of NMOS NMOS transistor
A Simple Switching Circuit variable DC voltage
Threhold Voltage Threshold voltage of T0
Design variable Library Setup
A Primitive Inverter Circuit Large VDS SATURATION Small VDS :Triode
Determine Region of Operation OFF SATURATION TRIODE
Determine Kn and Vth Need to select drain terminal in order to get current
Derivation • ID=0.5 unCox(W/L)(VGS-VTH)2 • Find VTH • SQRT(2ID/(unCoxW/L))=VGS-VTH • The VGS that yields 0 LHS is the threshold voltage • SQRT(ID)=SLOPE(VGS-VTH) • SLOPE=SQRT(0.5 unCox(W/L)) • This example: W/L=2um/1um=2 • SLOPE=SQRT(unCox)
To Calculate Kn,find SQRT(ID) The x interscept gives Vth Vth (this method)=150 mV Vth(Cadence)=164 mV
Find Kn=W/LunCox SQRT(ID) dSQRT(ID)/dVGS This curve implies that unCox depends on VGS!
Noise Margin Noise Margin: the maximum amount of noise at the input that can be tolerated before the output is affected significantly. attenuating attenuating amplifying dVout/dVGS NML NMH dVout/dVGS=small signal gain
Inverter In the Presence of Noise Relatively clean output 400 mV peak to peak noise Time Scaling Factor
Inverter In the Presence of More Noise 1 V peak to peak of noise
Noisy Input Relatively Clean Output
Adding a Capacitor to the Output RC time constant
Ring Oscillator 1nF oscillation