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Digital Integrated Circuits

Digital Integrated Circuits. Design Metrics. Mozafar Bag-Mohammadi. Design Metrics. How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function.

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Digital Integrated Circuits

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  1. Digital Integrated Circuits Design Metrics Mozafar Bag-Mohammadi EE141

  2. Design Metrics • How to evaluate performance of a digital circuit (gate, block, …)? • Cost • Reliability • Scalability • Speed (delay, operating frequency) • Power dissipation • Energy to perform a function EE141

  3. Cost of Integrated Circuits • NRE (non-recurrent engineering) costs • design time and effort, mask generation • one-time cost factor • Recurrent costs • silicon processing, packaging, test • proportional to volume • proportional to chip area EE141

  4. NRE Cost is Increasing EE141

  5. Total Cost • Cost per IC • Variable cost EE141

  6. Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com EE141

  7. Wafer Size EE141

  8. EE141

  9. Yield EE141

  10. Defects a is approximately 3 EE141

  11. Cost per Transistor cost: ¢-per-transistor 1 Fabrication capital cost per transistor (Moore’s law) 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1994 1982 1985 1988 1991 1997 2000 2003 2006 2009 2012 EE141

  12. Some Examples (1994) EE141

  13. Reliability―Noise in Digital Integrated Circuits V ( t ) v DD i ( t ) Inductive coupling Capacitive coupling Power and ground noise EE141

  14. V(y) V f OH V(y)=V(x) Switching Threshold V M V OL V(x) V V OL OH Nominal Voltage Levels DC OperationVoltage Transfer Characteristic VOH = f(VOL) VOL = f(VOH) VM = f(VM) EE141

  15. V out Slope = -1 V OH Slope = -1 V OL V V V IL IH in Mapping between analog and digital signals V “ 1 ” OH V IH Undefined Region V IL “ 0 ” V OL EE141

  16. Definition of Noise Margins "1" V OH Noise margin high NM H V IH UndefinedRegion V NM Noise margin low L IL V OL "0" Gate Input Gate Output EE141

  17. Noise Budget • Allocates gross noise margin to expected sources of noise • Sources: supply noise, cross talk, interference, offset • Differentiate between fixed and proportional noise sources EE141

  18. Regenerative Property Regenerative Non-Regenerative EE141

  19. v v v v v v v 0 1 2 3 4 5 6 Regenerative Property A chain of inverters Simulated response EE141

  20. N Fan-out N Fan-in and Fan-out M Fan-in M EE141

  21. R = ¥ i R = 0 o The Ideal Gate V out Fanout = ¥ NMH = NML = VDD/2 g=  V in EE141

  22. An Old-time Inverter 5.0 NM 4.0 L 3.0 (V) 2.0 out V V M NM H 1.0 0.0 1.0 2.0 3.0 4.0 5.0 V (V) in EE141

  23. Delay Definitions EE141

  24. R v out v C in A First-Order RC Network tp = ln (2) t = 0.69 RC Important model – matches delay of inverter EE141

  25. Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power: EE141

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