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Digital Integrated Circuits - week nine -

Digital Integrated Circuits - week nine -. Gheorghe M. Ş tefan http://arh.pub.ro/gstefan/ - 2014 -. Veitch-Karnaugh diagrams. m 0 = a’b’c’d ’ Are based on the minimal Hamming distance m 1 = a’b’c’d between adjacent cells m 2 = a’b’cd ’

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Digital Integrated Circuits - week nine -

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  1. Digital Integrated Circuits- week nine - Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

  2. Veitch-Karnaugh diagrams m0 = a’b’c’d’ Are based on the minimal Hamming distance m1 = a’b’c’d between adjacent cells m2 = a’b’cd’ m3 = a’b’cd m4 = a’bc’d’ m5 = a’bc’d m6 = a’bcd’ m7 = a’bcd m8 = ab’c’d’ m9 = ab’c’d . . . m15 = abcd Veitch version Digital Integrated Circuits - week nine

  3. Digital Integrated Circuits - week nine

  4. Karnaugh version Digital Integrated Circuits - week nine

  5. Minimizing logic functions smallest number, of rectangular surfaces of 1’s, with maximal area, containing 2i 1’s, and including all 1’s Digital Integrated Circuits - week nine

  6. “don’t care”s a’b +a’c b + c Digital Integrated Circuits - week nine

  7. V-K’s with included functions Is a two-step process: • Only 1’s • 1’s become “don’t’ care”s (bc’d + a’bc’ + b’c) + (acde + c’de’) Digital Integrated Circuits - week nine

  8. Transition diagrams Digital Integrated Circuits - week nine

  9. Moore version Digital Integrated Circuits - week nine

  10. Digital Integrated Circuits - week nine

  11. Mealy version Digital Integrated Circuits - week nine

  12. Verilog modules Immediate Moore version for ‘bb detector’ Digital Integrated Circuits - week nine

  13. State transition function: Digital Integrated Circuits - week nine

  14. Output transition function: For the delayed version: always @(posedge clock) case(state) init_state : out <= no; . . . Digital Integrated Circuits - week nine

  15. For the immediate Mealy version of ‘bb detector’ only the output function is different: For the delayed version the change is similar as for Moore version Digital Integrated Circuits - week nine

  16. Automata are complex circuits • The number of lines in the Verilog description: • Are equal with the number of states for the behavioral descriptions • Are equal with the number of gates used for the structural descriptions • The transition diagrams have the size in O(|Q| log |Q|) Because they are complex we must keep them small Digital Integrated Circuits - week nine

  17. State coding First coding Second coding Digital Integrated Circuits - week nine

  18. First version: Second version: Digital Integrated Circuits - week nine

  19. Coding styles • Minimal variation encoding: successive states are coded with minimal Hamming distance • Reduced dependency encoding: minimal Hamming distance for states preceded by the same state • Incremental encoding: whenever possible successive state are coded by incremented values • One-hot state encoding: one bit per state Digital Integrated Circuits - week nine

  20. Minimal variation encoding Digital Integrated Circuits - week nine

  21. Reduced dependency encoding Reduced dependency on both, X0 and X1 has no solution Digital Integrated Circuits - week nine

  22. Parasitic effects in automata • Automata with asynchronous inputs • Automata with asynchronous outputs • Hazard generated by asynchronous inputs • Propagation hazard • Dynamic hazard Digital Integrated Circuits - week nine

  23. Automata with asynchronous inputs If the input variable switches asynchronously the input of the state register can vary in the prohibited time – tsu + t+ +th • No problems if only one bit switches: 00 -> 01 => 00 -> 01 or 00 -> 00 • Big problems if more than one bit switch: 01 -> 10 => 01 -> 10 or 01 -> 00 or 01 -> 11 or 01 -> 01 The automaton evolves wrongly in the state space Digital Integrated Circuits - week nine

  24. The solution: reduced dependency state coding What can be done if there are state transitions depending on two or more asynchronous input variable ? Digital Integrated Circuits - week nine

  25. Asynchronous outputs:hazard due to asynchronous inputs Digital Integrated Circuits - week nine

  26. Digital Integrated Circuits - week nine

  27. Asynchronous outputs:propagation hazard Digital Integrated Circuits - week nine

  28. Avoiding propagation hazard Partial protection Full protection Digital Integrated Circuits - week nine

  29. Dynamic hazard Due to many-level combinational circuits (ex: carry propagation) Digital Integrated Circuits - week nine

  30. Fundamental limits • The asynchronous input bits can be considered only independently in distinct states • Immediate Mealy automata with asynchronous inputs can not have actual implementations (unpredictable outputs) • Delayed Mealy automata with asynchronous inputs can not have actual implementations (the state and outputs could evolve uncorrelated) • Hazard free Moore with asynchronous inputs have no actual solution (state must be encoded simultaneously with minimal variation and reduced dependency) Digital Integrated Circuits - week nine

  31. Home work 9 Problem 1: Digital Integrated Circuits - week nine

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