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STEIN Intro Davin Larson Space Sciences Laboratory University of California, Berkeley

STEIN is a SupraThermal Electron, Ion, Neutral sensor with an energy range of 2-300 keV and a resolution of 1 keV FWHM. It provides energy-angle response for electrons, ions, and neutrals, with symmetric response for ions and separate measurements for neutrals. This sensor is designed for space sciences applications.

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STEIN Intro Davin Larson Space Sciences Laboratory University of California, Berkeley

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  1. STEIN Intro • Davin Larson • Space Sciences Laboratory • University of California, Berkeley

  2. STEIN (SupraThermal Electron, Ion, Neutral) sensor Energy range: ~2-300 keV Resolution: ~ 1keV FWHM Field of view ~15º x70º

  3. CINEMA (Cubesat for Ions, Neutrals, Electrons, MAgnetic fields)

  4. Energy-Angle Response for Edge Pixels

  5. Energy-Angle Response for Middle Pixels

  6. Center Pixel Response (Electrons) Edge Pixel Response (Electrons) Deflection Voltage Left Sweep Right Sweep 4 kV 1.5 kV 600 0 600 1.5 kV 4 kV • Symmetric response for ions • Neutrals measured in center pixel – cleanly separated for energies below ~15-20 keV • Logarithmic voltage sweep with ten steps from 600V to 4 kV is optimal for • covering phase space. Need positive and negative sweeps to get all angles, • so 20 voltage steps desired.

  7. Estimation of Circuit board area

  8. STEIN Preamp Schematic

  9. STEIN Preamp Schematic

  10. STEIN Preamp Schematic

  11. STEIN Shaper Chain (1 of 4)

  12. STEIN – DACs / Actel schematic

  13. END of PRESENTATION

  14. Replace parallel plates with Series of blades STEIN Testing • New deflector plates • Built and installed (1 of 2) • Test (planned) on 2010/1/9

  15. STEIN • STEIN ETU on Manipulator

  16. STEIN Electron Calibration Setup VD Cr Layer STEIN Mounted on 3-axis Manipulator Quartz window D0 D3 D2 D1 Electron Beam Pen-ray UV Lamp yaw angle -V Delrin Insulator Vacuum chamber (grounded)

  17. n p Solid State Detector Basics Avg signal in black Real signal in red +35 V Outside at bias Voltage PH Voltage Charge Voltage 2us 2ns Time Time Time Shaper Example: 3.6 keV Particle strikes detector CSA -+ Minimize distance The shaper circuit averages out the “noise” guard ring ~200A Al ~200A Poly Si It takes 3.6 eV to make one electron-hole pair Total charge produced is: N = 3600 eV /3.6eV = 1000 electrons = 1.6e-16C Output PH is proportional to deposited energy! 300 micron thick detector

  18. Solid State Detector Basics (Cont) DAC PH Voltage Thresh FPGA (logic) Convert signal occurs when THRESH is high and PD passes through zero 2us Comparator Time Read Shaper Shaper Signal ADC Convert The shaper circuit averages out the “noise” PD Zero crossing Differentiator Comparator Convert Memory Thresh 2us Signal Voltage PD 300 micron thick detector Time

  19. single 4keV electron 2 simultaneous 4 keV electrons

  20. Response to Electron gun sweep Count rate during electron gun sweep Benefits of automation: It is extremely useful to collect data continuously and plot history of measurements. Note slight increase in electron beam intensity and hysteresis effect between ramp up and ramp down. Triples Doubles Singles ADC channel not symmetric Time 

  21. 15 keV constant electron beam Deflector YAW angle

  22. Detector response vs Yaw angle Yaw angle Scattered e-’s D1 D2 D3 D0 Total counts D1 D2 D3 D0

  23. < System Name > Agenda • AGENDA Overview Requirements Design <Test Results if any> Development Plan Issues

  24. Processor Board Combined LVPS/Logic Overview EXAMPLE ONLY

  25. Requirements EXAMPLE ONLY

  26. PIC – UHF (UART) PIC – EPS ( I2C ) PIC – SD card (SPI) PIC – FPGA (SPI & I2C) Design SD CARD FPGA – Tx (bitsteam) FPGA – STEIN (CDI) FPGA – MAGIC (SPI) • Data Flow Specifications • Tx : 1 Mbps continuous • SDCARD : 1.28 Mbps Write, 1 Mbps Read (min) • STEIN: 16 bits/event, 80KHz events = 1.28Mbps • MAGIC: 20 bits x 20 Hz x 3 axes = .001 Mbps • UHF: 0.0096 Mbps EXAMPLE ONLY

  27. Development Plans • Development • Pumpkin Development Board + Laptop PC • MPLAB30 “C” Compiler, Simulator, Debuggers • Subversion (SVN) for storing source code and documents • GSE Laptop running GSEOS • FSW Developed in phases: • CPU/Mother Board Only • CPU/Mother Board + [EPS, Batt, UHF, IIB] • CPU/Mother Board + [EPS, Batt, UHF, IIB] + [HVPS,STEIN, MAG] • Verification Matrix Provides Status of Requirements • Comprehensive Performance Test on Development Board • Load into Flight System • Joins CINEMA Test Flow and Quality reporting EXAMPLE ONLY

  28. Issues • CPU • Floating Point Mult/Div/Add performance#’s needed • Memory Very Small (especially 2K DMA area) • Pumpkin RTOS not useful for FSW EXAMPLE ONLY

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