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Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny. . Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel. QNoC. Research. Group. Hierarchical NoCs . PyraMesh
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Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip Ran Manevich, Leon Polishuk, Israel Cidon, and Avinoam Kolodny. Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel QNoC Research Group
Hierarchical NoCs PyraMesh • R. Manevich, I Cidon and, A. Kolodny. “Handling global traffic in future CMP NoCs” SLIP 2012. Hybrid Ring/Mesh S. Bourduas and, Z. Zilic, “Latency reduction of global traffic in wormhole-routed meshes using hierarchical rings for global routing.” ASAP 2007.
Hierarchical NoCs lower hop distances PyraMesh10 Hops 2D Mesh 14 Hops
Max. Hop distance vs. Number of Modules Who is right? LONG LINKS Go Go Hierarchical NoCs!!!
Parallel link delay model Repeated wire [Bakoglu - 1990]: Elmore’s delay:
Links delay in 16x16 hierarchical NoC LONG LINKS Short 1 mm Medium 1.9 mm Long 3.4 mm 16x16 Mesh.8x8, 4x4 Upper Levels 29 nm Technology Elmore’s Delay –Unrepeated, min. size global links (ITRS): ~17mm Short: 0.11ns Medium: 0.41ns Long: 1.31ns 12X 300 mm2 die
Adjusting delay of parallel links Repeaters insertion: Lower wire delay by inserting repeaters. Wire sizing: Lower RC delay by changing wire pitch (S and W).
Wire design parameters ΛS– Scaling of S vs. min. size global wire ρ - Density of repeaters per millimeter SR – Repeaters’ size normalized to Bakolu’s optimal size ΛW– Scaling of W vs. min. size global wire [ITRS].
Cost of adjusted links WC = 2 WC = 1 WE USE 2X Min. Pitch Min. Pitch Power Cost - Unified cost function - Wiring Cost -
Finding lowest cost wires for target frequency Shuffle multiple design configurations (Monte-Carlo). For the target frequency, place each configuration on “Cost Function (CF)-Link Length” plane. Lowest cost configurations along the Pareto curve.
Lowest cost links – 29nm-8nm technology nodes Max. achievable single cycle lengths – 29nm Max. achievable single cycle lengths – 20nm
Max. achievable link length for different target frequencies 3.4 mm Hierarchical NoCs with single-cycle long links are feasible at practical frequencies – it’s all a matter of cost.
Back to our example 1 mm 1.9 mm 3.4 mm Delayof wires at: 29nm, 17nm, 10nm Technology nodes Costof adjusting wires to: 1 GHz – 5GHz Target frequencies.
Our example – Delays of NoC wires before adjustements 1 GHz 2 GHz 3 GHz 4 GHz 5 GHz
Costs of adjusting wires to 1GHz Cost Function (CF) [%] <1% 1 GHz
Costs of adjusting wires to 2GHz Cost Function (CF) [%] <1% 11% 2 GHz
Costs of adjusting wires to 3GHz Cost Function (CF) [%] <1% 6% >1% 4% 39% 3 GHz
Costs of adjusting wires to 4GHz Cost Function (CF) [%] >1% 3% >1% 1% 19% >1% 19% 84% 4 GHz
Costs of adjusting wires to 5GHz Cost Function (CF) [%] >1% 1% 6% >1% 4% 39% 1% 36% 164% 5 GHz
Definition of cost overhead of adjusting long wires In our example (CF = Cost Function, l = length ): short – 1mm med – 1.9mm long – 3.4mm
Total length of each kind of links – our 16x16 NoC Hierarchical NoCs - Few long wires - Low overheadof adjusting them not to be a bottleneck.
Cost overhead of adjusting long wires – our 16x16 NoC 28 nm 65 nm 28 nm
Conclusions LONG LINKS • Are a minority. Go Go Hierarchical NoCs!!! • Are not that long! LONGER≠ LONG • Can be adjusted for single cycle at practical target frequencies with low system costs. NOT THAT LONG ! LONG Multi-cycle long links Single-cycle long links LONG LONG Long links in hierarchical NoCs: