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VIIT-GRAPES-3 COLLABORATION

VIIT-GRAPES-3 COLLABORATION. Dr. C. S. Garde Vishwakarma Institute of Information Technology, Pune. Background. Experimental Physics – Technology intensive Devising new Experiments using cutting edge Technology – a must for new Physics

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VIIT-GRAPES-3 COLLABORATION

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  1. VIIT-GRAPES-3 COLLABORATION Dr. C. S. Garde Vishwakarma Institute of Information Technology, Pune VIIT, Pune

  2. Background • Experimental Physics – Technology intensive • Devising new Experiments using cutting edge Technology – a must for new Physics • However, limited time and manpower for research in technology • VIIT has a large pool of engineering faculty (~130) and students (500 in final year) • Win-Win situation VIIT, Pune

  3. BE Projects with GRAPES - 3 • Design of Si Photo Multiplier (SiPM) • Field Programmable Gate Array (FPGA) based high speed counter • Power supply for SiPM • Photomultiplier tube DAQ • Web Interface for ROOT monitoring • Binary to ROOT conversion using ROOT framework • Inventory Management System for GRAPES-3 VIIT, Pune

  4. Statistics VIIT, Pune

  5. GRAPES-3 VIIT, Pune

  6. BE Projects with GRAPES - 3 • Design of Si Photo Multiplier (SiPM) • Field Programmable Gate Array (FPGA) based high speed counter • Power supply for SiPM • Photomultiplier tube DAQ • Web Interface for ROOT monitoring • Binary to ROOT conversion using ROOT framework • Inventory Management System for GRAPES-3 VIIT, Pune

  7. Design of Si Photo Multiplier (SiPM) VIIT, Pune

  8. Tool: Silvaco TCAD 2010 • Uses Maxwell’s and Poison’s equation. • Started with simulation of P-N junction diode structure in reverse bias mode.( APD is just P-N junction operated above breakdown voltage) • First Mesh was optimized and it is chosen as 0.01 microns at Junction. N+ P

  9. Simulations were done by varying n-type and p-type concentration,keeping other parameters fixed. • Effect on breakdown voltage was observed and results are plotted. • P-type concentration Varied from 1e15 to 1e17 • N-type concentration Varied from 1e18 to 1e20 • Each range was broken into 10 points , so total 100 simulations.

  10. Simulated E-FieldProfile and I-V Curve (for 75V Breakdown structure) Net Doping(/cm3)

  11. Electric Field profile Vs Bias voltage

  12. Fig. 2 Fig. 1 Breakdown voltage depends on concentration of lightly doped side, here p-type side .Plotted graph (Fig. 1) shows the similar relationship as given in theory. (Semiconductor Device Fundamentals - Robert Pirret)

  13. Practical doping • Till now structure simulated as a step junction (abrupt junction) which is ideal case • Practical methods of doping : Ion Implantation and Diffusion • Diffusion : a error-function doping profile. • Ion Implantation : a Gaussian doping profile.

  14. Net Doping Profile for Step ,Gaussian and error function

  15. I-V curve for different doping profiles

  16. Capacitance : Cathode current and capacitance

  17. Optical Simulation • Spectral Response • With appropriate biasing(reverse) diode is bombarded with light of various wavelength covering visible spectrum. • Current through diode is monitored and plotted as function of wavelength. • Transient Response • Optical pulse of very short duration is incident on surface of diode. • Diode’s response (rise time, fall time) is studied .

  18. Spectral Response at different biasing voltages In any optical simulation for simple n+ p structure, reflections from top surface is not considered

  19. Spectral response at various n+ depths • Depth of n-type region was varied from 0.1 to 2.5 um and spectral response was taken at every depth, keeping light intensity constant. • Results were plotted for 580nm wavelength. • Peak was observed at 0.3 um.

  20. Intensity Variation at various n+ depths • Simulations were also done by changing input light intensity at various n+ depths keeping wavelength constant at 580nm. • Exactly same results were obtained as of previous simulation,which confirms the results. • Plotted graphs show considerable increase in current at depth of 0.3um. • Penetration depth of silicon at 580nm is 2um, which can be confirmed by decline in currents at higher depths. Cathode current (A)

  21. Transient simulation( P-Spice) • We could not obtain Transient response in P-Spice environment,here Cathode current pulse( Green) is much smaller than Available photo current pulse, which is inappropriate. • Problem might be in migrating from ATLAS environment to P-Spice environment. • So, we decided to simulate transient response in ATLAS environment without external quenching resistance.

  22. At 75.25V – just at breakdown (Atlas) Rise Time=1.2ns Cathode Current(A) Input Optical Pulse

  23. At 75.27V – above the breakdown

  24. Temperature variations

  25. n concentration = 1e18p concentration= 6.3e15

  26. Variation of temperature coefficient with n type conc. As n concentration is varied temperature coefficient does not vary much (the graph shown above is zoomed in)

  27. Variation of temperature coefficient with p type conc.

  28. Parameters

  29. Towards new structure... • Till now we have simulated only simple p-n junction(device simulation) in order to understand effect of every parameter. • So we moved on to the more practical structure, which is made up of 4-5 layers.

  30. Gain=32 at Breakdown

  31. Future • Process simulation started • After fabrication, simulations can be fine tuned for development of full fledged SiPM

  32. Web Interface for ROOT monitoring VIIT, Pune

  33. ROOT Utility • Object-oriented program and library. • Developed by CERN. • Designed for particle physics data analysis. • In other applications such as astronomy and data mining. • Parts of the abstract platform are: • Graphical user interface and a GUI builder • Container classes • Reflection • C++ script and command line interpreter (CINT) • Object serialization and persistence

  34. Files Processed by ROOT in GRAPES-3 Experiment

  35. Current Practices • Recorded data sent to collaborators by post/courier in DVDs • Every collaborator needs to know and memorize various commands of root • Access to data is not instant, as DVDs sent every week.

  36. Our Goal

  37. To develop a system for web monitoring of ROOT data and remote execution of ROOT commands. • System will generate graphs, images and necessary information required by collaborators of TIFR for analysis of data depending upon input provided by user through GUI.

  38. Sample GUI for Weather Weather PARAMETER BIN SIZE (minutes) TIME RANGE Start Date Time Temp (In) Default End Date Time Temp (Out) Pressure Humidity Rain Weed Speed PLOT

  39. Use Cases

  40. Our Approach

  41. Data Workflow

  42. Concluding Remarks • As a result of VIIT-GRAPES-3 collaboration, VIIT students are motivated to take up research careers • VIIT faculty also benefiting from hands-on experience • Developing valuable Human Resource • Strong VIIT-GRAPES-3 collaboration could help GRAPES-3 to upgrade the existing experiments and possibly take up new challenging experiments VIIT, Pune

  43. Thank You VIIT, Pune

  44. FPGA Based Network Enabled High Speed Event Counter

  45. AIM • Pulse signals from the Scintillator Detectors are digitized in the discriminator section and fixed width pulse is taken as an output • High Speed Event Counter takes these fixed width pulses as inputs and counts the number of such pulses • With the counting of these pulses duration of air showers can be determined and trigger control signals can be generated

  46. AIM

  47. FEATURES OF H.S.E.C. • High Speed Event Counter (HSEC) keeps the flexibility of varying the fixed pulse widths and can measure as low as 50 nsec pulse widths • Presently, the HSEC is tuned to count pulses of 70 nsec width • HSEC has 64 channel input capability • The counting logic is implemented in an FPGA (Spartan6-LX9) and the count value is stored temporarily in the memory unit in the FPGA • The count values of all channels are then accessed by the micro-controller from time to time

  48. FEATURES OF H.S.E.C. • The micro-controller is LPC2478 which has an ARM7-TDMI core, which is presently among the high-end microcontrollers • The ARM7 has its own built –in Ethernet MAC containing a fully featured 10/100 Mbps Ethernet connectivity • In the H.S.E.C. the count value accessed from the FPGA is then encapsulated at various levels of the TCP/IP stack and then sent over the Ethernet • The TCP/IP stack is intended to be a lite version which implements required protocols and ensures good connectivity, error checking and correction and flexibility in implementation

  49. FEATURES OF H.S.E.C. • A GUI is provided in Linux that only displays the received count value with respect to the channels • The ARM7 micro-controller has various other communication capabilities including UART, CAN, USB, USB-OTG, I2C and SPI • As a flexible solution to other projects as well , these communications are provided on the H.S.E.C. • As an example of flexibility, the USB feature can be used for debugging errors in the program without the need to uninstall the H.S.E.C. from the field site

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