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VIIT-GRAPES Collaboration

VIIT-GRAPES Collaboration. C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune. VIIT-TIFR collaboration. VIIT students in TIFR. Software Projects. Hardware Projects. 32 Channel FPGA Based Counter. Last year:

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VIIT-GRAPES Collaboration

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  1. VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune

  2. VIIT-TIFR collaboration

  3. VIIT students in TIFR

  4. Software Projects

  5. Hardware Projects

  6. 32 Channel FPGA Based Counter • Last year: • 32 channel 24 bit high-speed counter implemented on a Actel FPGA (counter and digital logic part) • FPGA and PIC micro-controller interfacing done • Data logging to PC by a PIC micro-controller via USB protocol (Linux compatible)

  7. 32 Channel FPGA Based Counter • This year: • FPGA programming – VHDL to Verilog conversion is in progress (small Verilog programs (counter, etc.) implemented and tested on hardware) • Pulse width measurement logic under development • New counter logic development in Verilog is in progress

  8. 64 Channel FPGA Based Counter (Scalar) • Last year: • Simulations of 32 bit 64 channel counter • 4 channel 16 bit Counter (Scalar) implementation on SPARTAN3E FPGA using VHDL • Data transfer to PC through ARM7 controller, via Ethernet protocol (UDP/IP) demonstrated • Multi-board configuration (IP Address based) with 2 ARM boards • Multi-threading approach demonstrated for data reception on PC

  9. 64 Channel FPGA Based Counter (Scalar) • This year: • FPGA programming – VHDL to Verilog conversion is in progress • 4 channel 4 bit counter demonstrated SPARTAN3E FPGA in Verilog • Automated approach to toggle between 64 channels is demonstrated • Multi-board configuration: synchronization of boards with I2C protocol demonstrated for 2 ARM Boards • Time stamping with milliseconds accuracy is demonstrated • Pulse width measurement logic under development • Ethernet part : Data transfer with TCP/IP protocol is under development

  10. High Voltage Data Acquisition System • Last year: • 48 channels system for PMT voltage monitoring developed • 1 V resolution in 2500 V • This system tested on actual PMT setup at CRL, Ooty • Data logging via USB every 5 sec

  11. Block diagram

  12. High voltage monitoring

  13. High Voltage Data Acquisition System • This year: • Different protection Circuits for already developed high voltage data acquisition board being developed and tested • Temperature, Humidity etc. sensors being tested for inclusion in high voltage data acquisition board

  14. Design and Implementation of Multiple Panels Solar Power System • Last year: • Maximum Power Point Tracking (MPPT) based charger developed for 25W solar panel • Data logging system (Voltage, Current, Power) for a single solar panel developed (via USB protocol)

  15. Design and Implementation of Multiple Panels Solar Power System • This year: • Improvement on MPPT charger circuit • Inclusion of Buck-Boost converter for high efficiency • Multiple Solar Panel Configuration with Data logging • Different Protection Circuits inclusion • Temperature Sensing

  16. Design and Implementation of Multiple Panels Solar Power System • This year:- • Design of solar power system for 1kW of power with 4 solar panels and 8 batteries. • Design of a Buck Boost Converter. • Design of a Isolated Boost Converter. • To design a Load Sharing System.  • Specifications of PV Panels :- • Voc for each panel = 42V • Isc for each panel = 7.6A • Vmpp for each panel= 35.25V • Impp for each panel=7.4A

  17. I2C based multiple FPGA Configuration • Started from this year • Counter based projects uses FPGA, so in future a multiple FPGA configuration will be needed • Multiple FPGA’s (slaves) will communicate to PIC based microcontroller (master) via I2C protocol • PIC micro-controller to PC communication via USB is developed previously and used for various projects

  18. High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier

  19. Silicon Photo-Multiplier (SiPM) • Multi-pixel semiconductor Avalanchephotodiode. • A Solid State Device • Operating voltage (30-120V) • Resolution - Single photon detection • Response time – ~1 ns • High gain - • High Quantum Efficiency – 90% • High Photon Detection Efficiency – 60% FIIG, University of Pisa, Italy

  20. SiPM Biasing

  21. Specifications of Power Supply * Also, total power supply unit should be as small as possible.

  22. Temperature Compensation Test SiPM • First Passive Compensation is done for proof of principle • SiPM typical temperature coeff. = 50 mV/˚C • LM 35 temp. Coeff. = 10 mV/˚C • A Circuit is connected to SiPM supply directly, that will change the supply voltage ground according to temperature

  23. Test Setup for Compensation test Compensation Circuit SiPM VME Test Setup SiPM Power Supply Data logger for Temperature measurement Blower (Heat) PC

  24. Results of Compensation Required Compensation is a non-linear Function

  25. Block Diagram for Proposed Power Supply High Voltage Generation (Voltage Multiplier Chain) PC USB Control Unit (Micro-controller) Voltage Regulation Scheme Temperature Sensors DAC Current Sense SiPM

  26. Test Board

  27. Tests Performed • DAC Stability • Line Regulation • Load Regulation • Linearity • Time Drift • Capacitor for Noise elimination at output and stability

  28. DAC Stability 5.102 uV variation in 5 V

  29. Line Regulation 0.04113% for 10% change in line voltage 0.03% for 20% change in line voltage

  30. Load Regulation No load to Full load (100uA) Best 0.6025% Channel 2 Worst 1.55% Channel 8

  31. Linearity

  32. Time Drift (Channel 1) Supply Voltage Regulator Output

  33. Time Drift Error Plots Supply Voltage Error Plot Regulator Output Error Plot 600 mVp-p change 100 mV change

  34. Ceramic Capacitor for reducing ripple • Where • Iout = 100 uA, dc = 0.98 • fsw = 19.52 (in KHz), Vp = 1 mV • Cmin = 0.0995 uf • C1 = 0.1 uf , C2 = 0.01 uf

  35. Time Drift (Improved) with 0.1 f Capacitor Channel 1 Without Capacitor With 0.1 uf Cap 15 mV Change

  36. Histograms

  37. Comparison Between 0.1f and 0.01f

  38. Histograms

  39. Voltage Generation (Voltage Multiplier) • A simple 10-stage Voltage multiplier chain is build with diodes (1N4148) and capacitors (0.22 F) • The chain is tested for input frequencies 50 Hz to 5 MHz and for sine and square inputs.

  40. Chain testing

  41. Specifications achieved on test board A stability of 10 mV in 50 mV resolution is achieved

  42. Conclusions • Software project: Except Parallelization of CORSIKA all other software projects have been partially implemented and are being fine tuned • Hardware projects: • Standard PIC micro-controller based USB has been standardized • ARM7 based Ethernet - UDP implemented, TCP in advanced stage • FPGA – VHDL to Verilog transition made, 32 channel counter in advanced stage, 64 channel also in good shape, I2C in initial stage • High Voltage Monitoring – Advanced stage • Solar PV – R&D on Multiple panel, high power system optimization • SiPM power supply – In advanced stage

  43. Guides from VIIT • C S Garde - Coordinator • V M Aranake • M S Karyakarte • S J Thaware • K J Raut • Mrs S Y Desai

  44. Guides from TIFR • S K Gupta - Coordinator • S R Dugad • Atul Jain • Jagdeesan • Mohanty • Hariharan • Raghunandan • Sarah • Serin • Suraj

  45. Students (Computer) • Mustafa Adib • ModakAmeya • MaratheAmogh • RachitKulshrestha • ShushuptiAjmire • TejasviBelsare • DhawalPriyadarshi • Ms Devanshi Shah • Shubham Gupta • Irom Ajay Singh • KishanRao • TejasRao

  46. Students (IT) • QaidjoharJawadwala • Harsh Kundnani • DyaneshwarKothule • Ms ShivangiHiray • Ms RekhaSangwan • RunaGaneshan • AyushiTripathi • AnkitBhavsar • Nikhil Mantri

  47. Students (Electronics) • AdityaGodbole, Veronica D’Souza, Saumitra Kale • AkshayManjare, DigvijayTambhale, ShefaliRai • AfshanShaikh, AkhilKurup, SyedShadab • KamleshShinde, BhagyashreeKalaskar, S Venkatesh • Ravi Prakash, Vinit Shah, SanketDahiwal • JaydeepKshirsagar, KushalKshirsagar • PankajRakshe (ME)

  48. Thank you

  49. Work Plan

  50. References [1] K.C. Ravindran, “Silicon Photo-multiplier development at GRAPES- 3”, WAPP workshop, CRL, Ooty. [2] BajarangSutar, “A talk on study of characteristics of SiPM”, TIFR, Mumbai. [3] R. Bencardino, J.E. Eberhardt, “Development of a Fast-Neutron Detector With Silicon Photomultiplier Readout”, IEEE Trans. On Nuclear Science, 2009

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