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WindLDR 5.3 and MicroSmart Pentra Firmware 210 New Features

WindLDR 5.3 and MicroSmart Pentra Firmware 210 New Features. WindLDR 5.3 and Firmware 210. Firmware 210 Modbus TCP/IP Supports Communication Port 1 Upgrades User Program Protection Upgrades Key Matrix Input

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WindLDR 5.3 and MicroSmart Pentra Firmware 210 New Features

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  1. WindLDR 5.3 and MicroSmart Pentra Firmware 210 New Features

  2. WindLDR 5.3 and Firmware 210 • Firmware 210 • Modbus TCP/IP Supports • Communication Port 1 Upgrades • User Program Protection Upgrades • Key Matrix Input • New instructions (XCHG, INC, DEC, SUM, RNDM, DJNZ, NDSRC, TADD, TSUB, HTOS, STOH, and HOUR) • Simulation mode Enhancements • User communication via a COM port of PC • Offline Communication Test • FA2J/3S to FC5A Program Conversion Aid

  3. Modbus TCP/IP • MicroSmart Pentra now supports Modbus TCP/IP • Port 1 supports Modbus TCP/IP Slave (Server) • Port 2 supports Modbus TCP/IP Master/Slave (Client/Server) Modbus TCP Master (FC5A as master) Modbus TCP Slave (FC5A as slave) Function Area Settings dialog box • Notes: • FC5A Modbus TCP/IP master supports 1:1 communication only • FC5A Modbus TCP/IP communication requires Web Server module (FC4A-ENET) Modbus TCP/IP settings

  4. Communication Port 1 Upgrades • Communication protocol on Port 1 can be switched to Maintenance protocol by storing value 1 to data register D8007 No Pins 6 and 7 are open Maintenance protocol Yes Yes D8007 is 1 Maintenance protocol No User protocol, Modbus protocol, or MODBUS TCP protocol • Modbus RTU/ASCII Slave and Modbus TCP/IP Slave are supported New options Notes: RS232C is available on Port 1

  5. User Program Protection Upgrades • New protect option making it impossible to upload program from MicroSmart Pentra Caution: It is impossible to upload program from PLC if “Prohibited” settings is used. This is to ensure 100% protection of intellectual property. To disable this feature, an empty program needs to be download to the MicroSmart Pentra. New option

  6. Key Matrix Input (1) • The key matrix input can be programmed to form a matrix with inputs and outputs to multiply input capabilities • A maximum of 1280 inputs can be read with 5 sets of key matrix inputs Example Following diagrams show an example of Key Matrix Input of 5 inputs and 3 outputs. 15 Inputs are stored in internal relays starting from the internal relay specified.

  7. Key Matrix Input (2) Wiring Example Pictures below show an example of Key Matrix Input circuit. 4 inputs and 5 outputs are used to form 20 key matrix inputs. DC power supply FC5A Terminal block Key Matrix Inputs circuit Key matrix inputs circuit (Back) Key matrix inputs circuit (Front) Key matrix inputs

  8. INC, DEC, and XCHG • INC (Increment) When input I0 is turned on, values in D10 is incremented by one. • DEC (Decrement) When input I0 is turned on, values of D20 is decremented by one. • XCHG (Exchange) When input I0 is turned on, values in registers D20 and D24 designated by operands D1 and D2 are exchanged with each other.

  9. RNDM (Random) and SUM (Sum) • RNDM While input is on, pseudorandom numbers between S1 and S2 are generated and stored in D1. Example When input I0 is turned on, RNDM is executed to generate a pseudorandom value ranging between 1 and 6. • SUM While input is on, N blocks of data starting at S1 are added and the result is stored to D1. Example When input I0 is turned on, D0 thru D3 are added, and the result is stored in D100.

  10. DJNZ • DJNZ (Decrement Jump Non-zero) When M10 is turned on, ADD instruction is executed 100 times. 100 is stored to D1 as the number of repeat cycle. ADD(W) is executed 100 times. When DJNZ is executed, D1 is decremented by one, and the program jumps to LABEL 127 if D1 is not 0.

  11. NDSRC • NDSRC (N Data Search) When input is on, a value S1 is sought in data registers starting with the data register S2. S3 specifies the quantity of data registers to search. Offset to the first match and quantity of matches are stored in D1 and D1+1.

  12. Time Addition and Subtraction When input is on, time data S2 are added/subtracted from date/time data S1, depending on the selected mode. The result is stored to D1. Mode 0 (Time) +/- Mode 1 (Date and Time) Day of week is calculated automatically +/-

  13. Sec and HMS conversion • HTOS When input is on, time data S1 in hours, minutes, and seconds is converted into seconds, and the result is stored to D1. • STOH When input is on, time data S1 in seconds is converted into hours, minutes, and seconds, and the result is stored to D1.

  14. HOUR (Hour Meter) • HOUR While input is on, the ON duration is measured. The measured time value (hour, minute, and second) is stored to 3 consecutive data registers starting from D1 and compared with the preset value S1. When the D1 value reaches the S1 value, D2 is turned on. Example Preset values On duration • Application • This instruction can be used to measure any kind of durations, such as operating hours.

  15. Simulation Mode (User Protocol) User protocol (TXD & RXD) simulation is supported using a COM port of PCs. BarcodeReaders Temperature Controllers PC Inverters WindLDR Simulator , , , or … COM Port • TXD & RXD instructions can be tested without actual PLCs. • Simulation Settings dialog box is added. When Port 2 is selected, TXD2 & RXD2 instructions are simulated. Select which port of the PLC to simulate

  16. Simulation Mode (Offline Test) • The communication of the PLC simulator can be tested without actual devices. • Communication Test Data dialog box PC WindLDR When clicking on Send button, selected data is sent to the simulator. PLC Simulator The communication test data can be created The reply from the PLC simulator.

  17. FA2J/3S to FC5A Program Conversion Aid • New instructions of FC5A version 210 are supported JINC, JDEC, and DJNZ of FA Series PLCs can be replaced to INC, DEC, and DJNZ of FC5A respectively • New Option for I/O Shifting (1) Inputs and outputs are shifted if I/Os don’t exist on the CPU module. For example, in case of FC5A-D32, it doesn’t have I20-I27 and Q20-Q27. I20- and Q20- are shifted to I30- and Q30- respectively. (2) Inputs and outputs on the CPU module are not used. I0- and Q0- are shifted to I30- and Q30- respectively. (1) (2)

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