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Spacer Lithography

Spacer Lithography. EE C235 Tim Bakhishev. Spacer Process. Pattern [Dummy] Gate. Deposit Conformal SiO 2. SiO2. Dummy. Poly-Si. Si - Substrate. Isotropic Etch of SiO 2. [Remove Dummy Gate] . Feature Size. Advantages of Spacer Process. Feature Size Conformal Deposition

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Spacer Lithography

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  1. Spacer Lithography EE C235 Tim Bakhishev

  2. Spacer Process Pattern [Dummy] Gate Deposit Conformal SiO2 SiO2 Dummy Poly-Si Si - Substrate Isotropic Etch of SiO2 [Remove Dummy Gate] Feature Size

  3. Advantages of Spacer Process • Feature Size • Conformal Deposition • Good Control of Film Thickness • Double Feature Density • Reduced Variation Drawback: One Line Width Can be worked around ! Y.K. Choi, et al “Spacer Patterning Technology for Nanoscale CMOS”, TED 2002

  4. FinFET Process Flow LPCVD PSG as thin as 10nm Sacrificial SiGe Remove SiGe S/D Pad Mask After Gate Formation Large Line Width Mask (optional)

  5. UTBFET Process Flow LPCVD PSG as thin as 10nm Sacrificial SiGe Spacer Mask Final Spacer After Gate Formation Gate Pad and Large L Mask

  6. Double/Quadruple Fin Process Standard (Double) Fin Active Layer Pattern SiGe Pattern Spacer Formation SiGe Removal Quadruple Fin Active Layer Pattern Second Spacer S/D Mask R. Rooyackers, et al “Doubling or quadrupling MuGFET fin …”, IEDM 2006

  7. Conclusion • Advantages: • Greatly Scaled Feature Size • Improved CD Uniformity • Possibilities Beyond Lithography With Gate With S/D Pads • Drawbacks: • Process Complexity • Layout Concerns • Highly Selective Etch Processes Necessary

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