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S U R R E Y S A T E L L I T E T E C H N O L O G Y L I M I T E D

S U R R E Y S A T E L L I T E T E C H N O L O G Y L I M I T E D. FPGA Implementation of Sine and Cosine Generators using the CORDIC Algorithm. Tanya Vladimirova and Hans Tiggeler S urrey S pace C entre University of Surrey, Guildford, Surrey, GU2 5XH Tel: +44(0)1483 879278

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S U R R E Y S A T E L L I T E T E C H N O L O G Y L I M I T E D

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  1. S U R R E Y S A T E L L I T E T E C H N O L O G Y L I M I T E D FPGA Implementation of Sine and Cosine Generators using the CORDIC Algorithm Tanya Vladimirova and Hans Tiggeler Surrey Space Centre University of Surrey, Guildford, Surrey, GU2 5XH Tel: +44(0)1483 879278 Fax:+44(0)1483 876021 email: T.Vladimirova@ee.surrey.ac.uk, H.Tiggeler@ee.surrey.ac.uk

  2. Outline of Presentation • Introduction • Implementations • Algorithms • Redundant Adder • Synthesis Results • Application • Conclusion • Questions

  3. Introduction Surrey Space Centre (SSC) 12 micro satellites launched 3 ready to be launched 50/300Kg Communication and scientific missions

  4. CORDIC Principles

  5. Implementations

  6. SHIFT SHIFT N N N Sequential/Iterative CORDIC START DONE CLK COS(X) SIN(X) X Z FSM X REG Y REG Z REG N Zmsb ATAN LUT Dx Dy + + + +/- +/- +/- - - - Zmsb Zmsb Zmsb NEWX NEWY NEWZ

  7. Parallel/Cascaded CORDIC X 0.60725 0.00000 arctan(1) >>0 >>0 +/- +/- +/- + + + - - - arctan(0.5) >>1 >>1 +/- +/- +/- + + + - - - arctan(0.25) >>2 >>2 +/- +/- +/- + + + - - - Z COS(X) SIN(X)

  8. Redundant CORDIC Schemes

  9. Latency Comparison

  10. Redundant Adder

  11. Actel SX Synthesis Results Area Optimised 3500 4.5MHz 3000 2500 5.2MHz 1.9MHz 2000 Actmap 3.5.04 SX Module Count Synplify 5.1.4 22.3MHz Spectrum 5.69 1500 2.8MHz 1000 4.3MHz 5.2MHz 5.9MHz 500 0 12 14 16 24 32 12 14 16 Iterative Cascaded

  12. Actel SX Synthesis Results Delay Optimised 4000 4.5MHz 3500 3000 2500 5.2MHz Actmap 3.5.04 2000 Synplify 5.1.4 SX Module Count 1.9MHz Spectrum 5.69 2.8MHz 22.3MHz 1500 4.3MHz 5.2MHz 1000 5.9MHz 500 0 12 14 16 24 32 12 14 16 Iterative Cascaded

  13. Xilinx Synthesis Results Area/Delay Optimised 700 0.4MHz 600 500 3.1MHz 0.6MHz 400 Area CLB Module Count Speed 5.2MHz 300 5.3MHz 1.7MHz 200 1.9MHz 2.7MHz 100 0 12 14 16 24 32 12 14 16 Iterative Cascaded

  14. Application Computation of Legendre polynomials in the IGRF model (ADCS) Increase in speed 44% - 23% compared to s/w running on a 333 MHz Pentium Direct Digital Synthesis Suitable for high-speed designs - 22 Msps LUT but 50 Msps pipelined cascaded CORDIC CORDIC - sine and cosine at the same time

  15. pi 2 pi 2 Direct Digital Synthesis Not Required for CORDIC Must be scaled for CORDIC MSB SIN( X) Phase Increment Value X Phase to Amplitude Converter Register COS( X) Phase Accumulator LUT, CORDIC, ….

  16. sin(a+b)+cos(a+b) 2 sin(c).cos(a)-sin(c).sin(a) 2 cos(a+b)-sin(a+b) 2 sin(c).cos(a)+sin(c).sin(a) 2 Look-Up Table Approach Modified Sutherland Architecture Phase msb msb-1 a Coarse LUT +/- + COS(X) b Fine LUT c Coarse LUT +/- + SIN(X) Fine LUT sin(a+b+c) = sin(a+b).cos(c)+sin(c).cos(a+b) cos(a+b+c)= cos(a+b).cos(c) - sin(a+b).sin(c)

  17. Conclusion • A trade-off speed/area will determine the right • CORDIC FPGA implementation for an application • A 32-bit 1.9 Msps iterative Cordic can be • implemented in a small FPGA (Actel SX16-3) • A 12-bit non-pipelined cascaded Cordic runs at • 22.3 Msps (Actel SX16-3) - comparable to a LUT • Module count and operating speed depend • significantly on the used Synthesis Tool • Current rad-tolerant FPGAs are not dense enough for the cascaded and redundant approach

  18. Conclusion • Simulation has shown that the redundant adder can improve the efficiency of CORDIC FPGA implementations for bit-lengths higher than 32-bit

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