Testability in EOCHL (and beyond…)

1. Testability in EOCHL (and beyond…) Vladimir Zivkovic National Institute for Subatomic Physics (Nikhef), Amsterdam, The Netherlands FEI4_A review, 2-3rd November 2009 CERN, Geneve

2. Outline • Introduction • DfT Architecture • DfT Flow • Back-end Test Development • Future Work

3. Functional vs Structural Testing • Functional testing verifies that a circuit fulfils the desired spec. • Functional testing not feasible for exhaustive tests. • Example: 32-bit adder requires 265 ≈ 3.7*1019 test vectors • Structural test focuses rather on the circuit structure and can cover manufacturing defects that otherwise may not have been detected by functional testing. • Power or ground shorts • Open interconnect on the die (caused by dust particles) • Short circuited source or drain on the transistor, (caused by metal spike through)

4. Scan Chain DfT Principle

5. Outline • Introduction • DfT Architecture • DfT Flow • Back-end Test Development • Future Work

6. Digital Testing Framework • Stimulus and response calculated by Automatic Test Pattern Generator (ATPG) based on fault models • Computed on the whole device or on parts of the design, so-called embedded IP’s (cores) • Access to embedded terminals of the IP through design for test (DfT) is necessary 0110 1000 1011 0001 : comparators fail flags Device Under Test (DUT) stimuli 0001 0111 1010 0001 : response

7. IP IP source TestRail TestRail sink TAM TAM wrapper 2. Test Access Mechanism (TAM) 1. Test Pattern Source and Sink 3. Core Test Wrapper Generic Test Access Architecture [ Zorian, Marinissen, Dey - ITC’98 ] IP = {EOCHL, CMD, DOB, EODCL}

8. Wrapper bypass bypass TestRailoutputs TestRailinputs IP functioninputs function outputs Wrapper Control Block Wrapper Isolation Overview Mandatory Wrapper cells providing function access and test controllability + observability at IP’s data terminals TestRail access to wrapper cells (‘surround chains’) and IP flip flops (‘scan chains’) Optional Bypass register for all TestRail chains Wrapper Control Block+ anti-skew element

9. scan chain 0 (3000 FFs) scan chain 0 (1700 FFs) scan chain 1 (600 FFs) scan chain 1 (400 FFs) EOCHL CMD Wrapper Control Block Wrapper Control Block Wrapper EOCHL Wrapper CMD Top level Test Control IC LEVEL How does this reflect to our situation? Insert wrappers around EOCHL, CMD and other blocks with scan chains (DOB, EODHL) Primary TRO_cmd[0:2] TRI_eochl[0:2] TRO_eochl[0:2] TRI_cmd[0:2] Inputs from other digital blocks, e.g. EODCL, CFGMEM Outputs to other digital blocks, e.g. EODCL, CFGMEM Inputs from other digital blocks, e.g. EODCL, CFGMEM

10. Wrapper + Top Level Control • Blocks will be scan-tested independently, i.e. in isolation of each other • Top-level test control (scan enable, test mode selection) have to be implemented for each block Courtesy of M. Garcia-Sciveres *

11. Wrapper Isolation Cells Provide the application of the test stimuli at the embedded IP inputs as well as the observability at the embedded IP outputs

12. Wrapper Cells in the Nutshell Input isolation Output isolation Note: Only the combinatorial inputs require isolation

13. Outline • Introduction • DfT Architecture • DfT Flow • Back-end Test Development • Future Work

14. Two-pass Synthesis or mapped flow

15. Synopsys DfT Compiler Control Script (.tcl) Test Constraints (.tcl) Library Synopsys DfT Compiler Netlist (.v) Synopsys Internal databasel STIL/CTL test protocol ScannableNetlist (.v) Listings

16. DfT Procedures in the nutshell • PROC_dft_insert_init • Global setup for dft insertion • PROC_read_design • Reads netlists and libraries and builds the design • PROC_create_protocol_for_test • Invokes the test constraints and builds the test protocols • PROC_insert_scan • Insert scan chains (preview_dft and insert_dft) • PROC_handoff_design • Write result to verilog, db, and test model (STIL/CTL) files

17. Scan Chain reports for the EOCHL • 1 scan chain, length= 2927 • Standard DfT signals: si, so, se • Clocked with an additional test clock (tck) –clock gating with functional clocks performed at the top level of the IP • Additional DfT signal tm (to enable the test clock)

18. ATPG flow A plan is to use Synopsys TetraMax ATPG tool This flow has to be executed at the design level containing EOCHL, CMD and wrapper isolation

19. Test Patterns The TetraMax ATPG is expected to generate the following: • Continuity test patterns • To check the scan chain structures themsleves, typically 11101000 sequence is shifted through • Scan chain patterns for stuck-at faults Optionally: • IDDQ patterns • Transition/Path delay fault patterns • Bridge patterns

20. Outline • Introduction • DfT Architecture • DfT Flow • Back-end Test Development • Future Work

21. Test Assembly Process The main purpose is to: • Assemble the test patterns of the IP(s) in the IC • Convert these patterns into the real test vectors • Generate the test bench for the simulation with both stimuli and response • Include the timing and wave information

22. DfT Abstractions test lib Test patterns • waveform generation • functional test test bench netlist tester specific vectors behavior models Simulator Back-End Test Development Flow Test Assembly

23. Wafer Test DUT ATE, Test Setup Test Setup Lab Setup

24. Future Work concerning the test development flow with scan chains • Create the Wrapper around CMD and EOCHL blocks • Run the ATPG at this level • Back-end test development • Link to lab setup • Link to tester vectors running at tester platform (Verigy? Teradyne? Or … ?) • Mixed-Signal Test