S-ALTRO demonstrator design review meeting

S-ALTRO demonstrator design review meeting Eduardo Garcia

INDEX • Background: Block diagram, new functions and demonstrator communication protocol • Digital functionality • Design and verification • Synthesis • Power routing, Layout • Timing verification • Test benches on digital block • Testability features

Block diagram

What’s new in S-ALTRO respect to ALTRO • Optimize filters at the digital signal conditioner: • BC1: more precision at the baseline subtraction with 2 fractional bits precision. • DS: reduced to half size due to change in the architecture. • BC2: flexible MAF (move average filter) and optimized round off. • Reduce the read out time of the chip: • Full readout chip instruction (skipping empty channels). • New register containing information about empty channels • Localized switching noise: • The increase in the sampling frequency makes more important that the switching noise comes just from one of the clock edges (rising). • Other new features • Soft reset, restart the FMS and counters without reset the configuration registers. • Zero suppression threshold per channel. Filters thresholds per channel… Eduardo Garcia

Demonstrator BUS • 40 bi-directional lines. • 6 control lines. • 2 triggers lines • Global/Soft reset, Sampling and Reading clock. Based on ALTRO bus

Demonstrator BUS AD (Address/Data bidirectional buffer) ALTRO • Write register example: Inputs Output Eduardo Garcia

Demonstrator BUS Eduardo Garcia

Digital Signal Conditioner • The objective of the Digital Signal Conditioner (DSC) is to increase the efficiency of the data reduction algorithm (Zero Suppression). The DSC comprises three main building blocks: • First Baseline Correction (BC1): eliminates the low frequency perturbations and systematic effects. • Digital Shaper (DS): It can be used for two different applications; tail cancellation or pulse shaping. • Second Baseline Correction (BC2): removes non-systematic perturbations of the baseline that are superimposed to the signal. Eduardo Garcia

ALTRO validation Automatic Check (200ps window) Design and verification AALTRO netlist AALTRO TestBenches comparescan ٧ AALTRO Beh/RTL S-ALTRO design procedure. STEP 1. • Synthesizable • New functionality • New SRAMs 0 errors reported in the log file ٧ S-ALTRO RTL S-ALTRO TestBenches Eduardo Garcia

S-ALTRO design procedure. STEP 2. Synthesis and functional simulation. Design and verification 0 errors reported in the log file S-ALTRO netlist S-ALTRO TestBenches ٧ S-ALTRO design procedure. STEP 3. Back-annotated simulation. 0 errors reported in the log file S-ALTRO netlist S-ALTRO TestBenches ٧ Timing information from Encounter (minimum, typical, maximum) Minimum: 1.6V -55 C Typical: 1.5V 25 C Maximum: 1.4V 125 C Eduardo Garcia

S-ALTRO design procedure. STEP 4. Comparison. Design and verification Automatic Check S-ALTRO RTL S-ALTRO TestBenches Working on this comparescan S-ALTRO netlist Timing information from Encounter (minimum, typical, maximum) Eduardo Garcia

Synthesis RTL compiler • Timing constrains • 2 clock domains • Clock transition: 0.1ns • Input delay: 12ns • Output delay: 4ns • Max fanout all inputs: 1 • Max transition: 0.5 ns • Input transition all inputs: 0.5 ns • Clock uncertainty setup: 0.25 ns RTL code Gate level RTL compiler Encounter Eduardo Garcia

Synthesis RTL compiler Eduardo Garcia

INDEX • Background: Block diagram, new functions and demonstrator communication protocol • Digital functionality • Design and verification • Synthesis • Power routing, Layout • Timing verification • Test benches on digital block • Testability features Eduardo Garcia

Power plan Conditions: Static Analysis VDD = 1.5V sclk = 50MHz Rdoclk = 90Mhz Toggle probability: 0.3 Temperature: 25 C Voltage variation: 10% Signoff verification • Encounter Statistical Power Analysis: • Average power(considered in rail analysis): 118.62 mW • Worst IR drop peak: 7.2 mV • Max peak current: 19.856mA Eduardo Garcia

Layout • S-ALTRO digital block: 1460 µm 8560 µm Number of pads to be reduced/relocated for compatibility with the chosen package. Eduardo Garcia

Layout ٧ DRC ---------------------------------------------------------------------------------- --- RULECHECK RESULTS STATISTICS (BY CELL) --- CELL SHORT_IO_WRAPPER_CELL_7MA ... TOTAL Result Count = 2 (158) RULECHECK GRESD02_04_05_06 ... TOTAL Result Count = 1 (79) RULECHECK GRMA953 ............ TOTAL Result Count = 1 (79) CELL stack_shapes ................ TOTAL Result Count = 8 (632) RULECHECK GRESD19ab .......... TOTAL Result Count = 8 (632) CELL SIOVDD ...................... TOTAL Result Count = 1 (9) RULECHECK GRMA953 ............ TOTAL Result Count = 1 (9) CELL SIOGND ...................... TOTAL Result Count = 1 (9) RULECHECK GRMA953 ............ TOTAL Result Count = 1 (9) CELL SIODVDD ..................... TOTAL Result Count = 98 (1470) RULECHECK GRESD19aa .......... TOTAL Result Count = 97 (1455) RULECHECK GRMA953 ............ TOTAL Result Count = 1 (15) CELL SIODVSS ..................... TOTAL Result Count = 1 (14) RULECHECK GRMA953 ............ TOTAL Result Count = 1 (14) CELL SIOBRECVPD_7MA .............. TOTAL Result Count = 4 (8) RULECHECK GRESD19ab .......... TOTAL Result Count = 4 (8) CELL root ........................ TOTAL Result Count = 1014 (1014) RULECHECK GR40 ............... TOTAL Result Count = 2 (2) RULECHECK GR42a .............. TOTAL Result Count = 12 (12) RULECHECK GR131f_Mx .......... TOTAL Result Count = 1000 (1000) Standard cells Top cell Minimum density To be wave Eduardo Garcia

Layout ٧ LVS Known problem… Eduardo Garcia

Clock tree (Post routing) • Adcclk: • Rdoclk: • Min clk path (r/f): 1.87/1.87 ns • Max clk path (r/f): 2.16/2.09 ns • Rise skew: 290 ps • Fall skew: 220 ps • Min clk path (r/f): 2.05/1.82 ns • Max clk path (r/f): 2.38/2.12 ns • Rise skew: 330 ps • Fall skew: 300 ps Eduardo Garcia

Encounter Sign-Off timing analysis (Setup and Hold) • Timing constrains • 2 clock domains • Clock transition: 0.1ns • Input delay: 12ns • Output delay: 4ns • Max fanout all inputs: 1 • Max transition: 0.5 ns • Input transition all inputs: 0.5 ns • Clock uncertainty setup: 0.25 ns • Encounter Timing analysis: Sync clocks (40-80Mhz) • Sign-Off: Setup • Sign-Off: hold ٧ ٧ • Encounter Timing analysis: Asyncclocks (40-76.92MHZ) • Sign-Off: Setup • Sign-Off: hold ٧ ٧ Eduardo Garcia

Encounter Sign-Off timing analysis (Setup and Hold) Run again the optimization tool before continuing with the flow. Eduardo Garcia

Encounter timing analysis • Estimation of the clock limits: • Max rdoclk: ≈ 115 MHz • Max acdclk: ≈ 75 MHz Timing analysis from the output register to the pad From rdoclk: Max: 7.034 ns Skew: 1.467 ns Min: 5.567 ns SETUP (Worst case library) Eduardo Garcia

Test Benches • Interface • DSC • Test mode • Other test benches • Functional • Post-Layout ٧ ٧ These test benches don’t cover the 100% of the functionality, but many chip behaviors Eduardo Garcia

Test Benches • Functional test • Back-annotated Test bench Test bench Timing information RCU used for ALTRO design RCU used for ALTRO design ADC output ADC output S-ALTRO RTL S-ALTRO netlist Eduardo Garcia

TestBench 1:Writing and Reading all the registers. • TestBench 2:Filling the memory with a pattern (ramp pattern) and reading back the memory for 4 and 8 buffers. • TestBench 3:Writing and reading events. For this purpose, the following sequence of instructions is given: INTERFACE 1.- 2.- // 8 buffers // - EV1 (GOOD) // - EV2 (BAD) // - EV3 (BAD) // - EV4 (GOOD) // - EV5 (BAD) // - ReadOut EV1 // - EV6 (GOOD) // - EV7 (GOOD) // - EV8 (GOOD) // - EV9 (GOOD) // - EV10 (GOOD) // - EV11 (GOOD) // - EV12 (BAD) // - ReadOut EV4 // - EV13 (GOOD) // - EV14 (GOOD) // - EV15 (GOOD) It will be lost // - ReadOut EV6 // 4 buffers // - EV1 (GOOD) // - EV2 (BAD) // - EV3 (BAD) // - EV4 (BAD) // - EV5 (GOOD) // - EV6 (BAD) // - ReadOut EV1 // - EV7 (BAD) // - ReadOut EV5 // - EV8 (GOOD) // - EV9 (GOOD) // - EV10 (GOOD) // - EV11 (GOOD) // - EV12 (GOOD) It will be lost // - ReadOut EV8 // - ReadO EV9 // - ReadOut EV10 // - ReadOut EV11 // - ReadOut EV? No ReadOut possible // - ReadOut EV7 // - ReadOut EV8 // - ReadOut EV9 // - ReadOut EV10 // - ReadOut EV11 // - ReadOut EV13 // - ReadOut EV14 // - ReadOut EV? No ReadOut possible

TestBench 4: Test Broadcast , BC Selected. • TestBench 5: Parity Errors, Wrong Chip Address, Wrong Instruction. • TestBench 6: Test the soft reset. • TestBench 7: Pre-trigger, AllReadOut. • TestBench 8: Global reset. • TestBench 9: ADC testing block. INTERFACE Eduardo Garcia

TestBench 10: Test the BC1 memory • STEP 1. Fill the memory with a fixed pattern and read it • STEP 2. Test din-fpd • STEP 3. Test din - f(t) • STEP4. Test din - f(din) • STEP 5. Test f(din) - fpd • STEP 6. Test din - vpd – fpd • TestBench 11: Test of the DS • TestBench 12: Test of the BC2 DSC • TEST-MODE • TestBench 13: BC1 memory is filled with a pattern, created in Matlab, and used like test inputs for the DSC. Eduardo Garcia

TestBench 14: Send a trigger when reading the MEB, with single channel readout and full chip readout. Checked in the waveform output. Other test-benches • Clocks scenarios ٧ • Nominal: sclk = 40 MHz, rdoclk = 80 MHz • Slow sampling: sclk = 13 MHz, rdoclk = 80 MHz • Slow readout: sclk = 40 MHz, rdoclk = 60 MHz Metastability errors at simulation with some clocks, corners combinations Eduardo Garcia

INDEX • Background: Block diagram, new functions and demonstrator communication protocol • Digital functionality • Design and verification • Synthesis • Power routing, Layout • Timing verification • Test benches on digital block • Testability features Eduardo Garcia

Testability features • Without auxiliary pins: • The baseline memory can be used to generate a pattern to be injected into the processing chain for test purposes. Same than ALTRO test. Eduardo Garcia

Testability features • With auxiliary pins: • Data path input is multiplexed between the ADC outputs and 10 auxiliary pads common to all the channels. The multiplexor is configured from another pad. Eduardo Garcia

Future plans • Adapt the pads floorplan to the package chosen. • Run design flow with the new floorplan and check LVS, DRC. • Run the set of testbenches in the new netlist. • Have a look to the “conformal” test. Eduardo Garcia

X Conformal It doesn´t work… maybe one of the things to be checked in front of the computer. • **WARNING: Cannot find the VERPLEX_HOME environment variable! Eduardo Garcia

BACK UP… Eduardo Garcia

Spare cells Eduardo Garcia

Power plan Conditions: Static Analysis VDD = 1.5V sclk = 50MHz Rdoclk = 90Mhz Toggle probability: 0.3 Temperature: 25 C Voltage variation: 10% Signoff verification Eduardo Garcia

Power plan • RC (A): Resistor current; units are in ampere. filtered data range: 0.500mA - 42.269mA 27 values were in range 1: 16.000mA - 1.000GA 167 values were in range 2: 8.000mA - 16.000mA 199 values were in range 3: 4.000mA - 8.000mA 1508 values were in range 4: 2.000mA - 4.000mA 4228 values were in range 5: 1.000mA - 2.000mA 3515 values were in range 6: 0.500mA - 1.000mA Eduardo Garcia

First Baseline Correction (BS1) Systematic perturbation Baseline drift Fixed pedestal Systematic perturbation Slow drifts Combination fpd = 0 Eduardo Garcia

Digital Shaper (DS) This architecture has been optimized in terms of data-path width respect to ALTRO, but the methods used to obtain the Tail Cancelation Filter parameters in ALTRO are valid. Eduardo Garcia

Second Baseline Correction (BC2) • Operation bsl calculation bsl frozen After Tail Cancellation Filter After Baseline Correction II A fixed threshold can now be applied safely Double threshold BC II • Characteristics: • Corrects non-systematic perturbations during the processing time • Moving Average Filter (MAF) • Double threshold scheme (acceptance window) • 1. Slow variations of the signal  Baseline updated • 2. Fast variations of the signal  Baseline value frozen Eduardo Garcia

Zero Suppression (ZS) The Zero Suppression mechanism allows compressing the data stream by removing samples that are under this threshold. 1-Dimention above-threshold samples pre-samples post-samples fill-in samples rejected glitches discarded glitches dismissed samples Eduardo Garcia adjoined pre and post samples merged clusters

Encounter timing analysis Timing analysis from the output register to the pad SETUP Eduardo Garcia

Eduardo Garcia

S-ALTRO demonstrator design review meeting