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Effects of Variation on Emerging Devices for Use in SRAM

Effects of Variation on Emerging Devices for Use in SRAM. Greg LaCaille and Lucas Calderin. SRAM Power Consumption. Minimum operating supply voltage ( Vmin ) determined by: Minimum acceptable Ion/ Ioff ratio Effects of performance variation on read and write margins

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Effects of Variation on Emerging Devices for Use in SRAM

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  1. Effects of Variation on Emerging Devices for Use in SRAM Greg LaCaille and Lucas Calderin

  2. SRAM Power Consumption • Minimum operating supply voltage (Vmin) determined by: • Minimum acceptable Ion/Ioff ratio • Effects of performance variation on read and write margins • As CMOS is scaled down both these values typically get worse. • Reducing Vmin will lower power consumption • SRAM assist techniques typically target improving variation tolerance contribution. • Device selection can affect the contribution from leakage requirements.

  3. Fully Depleted CMOS • UTB-SOI or FinFET • Similar to Bulk CMOS • Gate control over entire channel reduces sub-threshold swing • DIBL reduced relative to Bulk but still present

  4. Carbon Nano-tube FETs • Ballistic transport • Saturation determined by contact resistance • Intrinsic channel more similar to BJT than MOSFET • Little-to-No DIBL

  5. Tunneling FETs • Band to Band tunneling current • Capable of sub-threshold swing < 60mV/dec • Low on current relative to MOS device of similar size • Little-to-No DIBL n-type

  6. SRAM Leakage • For a SRAM with m rows where A is the desired margin • m=256; A=4 • There is a minimum Vdd where this can be satisfied

  7. Read/Write Failure • Script written to simulate DC sweeps while sweeping variation in each transistor • Automatic detection of read and write failures

  8. Variation Limits • Each point represents a read or write failure • X axis is the average Vth of all the devices in the point that failed • Y axis is the rms sum of the difference in Vth for each device from the average Vth for the point • Area below the curve represents successful cells

  9. Variation Limits • For all devices the maximum allowable variation increased with Vdd as expected • The allowable deviation at the lowest Vth to satisfy leakage requirements deviates among the devices substantially

  10. Conclusion • Improved Ion/Ioff for the TFET doesn’t necessarily improve Vmin due to variation • CNFET is comparable to FD CMOS • Minimum access time will also play a key role in design of the SRAM • Any of these devices could be used with SRAM assist circuits to improve variability tolerance

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