“programmable Pattern generator” FINAL presentation

1. “programmable Pattern generator”FINAL presentation Students : Or Shperling & Liron Ulman Instructor : Ina Rivkin

2. Project’s Goals & Definitions • Designing an On-Line configurable “Pattern Generator” using 2 implementations: (1) Xilinx IP-Core DDS (Direct Digital Synthesizer). (2) A memory which will be use as a LUT for the pattern values, with a logic which will govern the memory output. • User’s trigger will initiate sine output. • Test the implementations on ML605 platform.

3. Project’s requirements (1) • Configuration phase- Inserting required Frequency and initial phase. • ‘Start’ initiates system iteration. Some delay after ‘Start’, our system is ready for trigger. • ‘Trigger in’ is 1KHz PRI [Pulse Repetition Interval]. • 1st ‘Trigger in’ initiates 4 channels of sine signal with different frequency and different phase. • Every ‘Trigger in’ reset the phase of all channels to the initial phase. • ‘Stop’ means : “End of current iteration”.

4. Project’s requirements (2) • Trigger_out is an output for the A/D to inform the Sine is ready. • Trigger_out(t) = Trigger_in+ delay = Trigger_in (t – (T1 + TDM ))T1 = Our module delay from triggerTDM = Analogue receiver delay • At least 32 sampling points per sine period. • Data width according to D/A width – typically 24 bits.

5. System Controller Our design sits on Virtex-6 FPGA STOP START TRIGGER_IN ML605 Board PINC_CONFIG POFF_CONFIG TRIGGER_OUT DATA_IN SINE0 SINE1 SINE2 SINE3 Receiver : Analog Pre- Processing D/A D/A D/A D/A A/D DSP Low Frequency

6. Frequencies analysis • Signal resolution and clock frequency dictates maximal sine frequency : • Our clock is produced by a DCM unit which is fed by 66 MHz board crystal’s “User Clock”. • We’ve examined some clock frequency till satisfactory results have been achieved.

7. Implementation • First Implementation – DDSUsing a built-in library unit- Direct Digital Synthesizer - to compute the sine. • Second Implementation- MemoryOur own implementation and logic design, using memory units and logic. • Each implementaion has 2 options: -Blocked memory-Distributed memory

8. Block Diagram

9. RESET Controller RESET 4 Channels Synthesizer (DDS/ Memory Design) Inputs Debouncer STATE_OUT RESET PINC_ CONFIG_DEB CE RESET CE SINE0 PINC_CONFIG PINC_ CONFIG SCLR SINE1 SCLR SINE2 POFF_ CONFIG_DEB WE WE POFF_CONFIG POFF_ CONFIG SINE3 REG_SELECT REG_SELECT START START_DEB PHASE_OUT0 START PHASE_OUT1 STOP_DEB STOP STOP PHASE_OUT2 TRIGGER_IN PHASE_OUT3 clk_sig CONFIG_DATA0 Configurator CONFIG_DATA1 Trigger Generator CONFIG_ DATA0 CONFIG_DATA2 RESET TRIGGER CONFIG_DATA3 CONFIG_ DATA0 RESET DATA_IN0 CONFIG_ DATA2 clk_sig DATA_IN1 DATA_IN2 CONFIG_ DATA3 RESET DATA_IN3 Programmable Delay DCM RESET RESET TRIGGER_OUT CLK_OUT TRIGGER_IN USER_CLK clk_sig clk_sig CLK_IN clk_sig RDY clk_sig RDY

10. Controller States Machine pinc_config_state poff_config_state POFF_CONFIG STATE_OUT = “001” STATE_OUT = “010” WE WE REG_SELECT = ‘0’ REG_SELCET = ‘1’ wait4trig_state PINC_ CONFIG STATE_OUT = “011” idle_ state START STOP STOP CE , SCLR STATE_OUT = “000” STOP reset_phase_state TRIGGER_IN run_state STOP State= “101” State= “100” TRIGEER_IN CE , SCLR CE STOP

11. Input • Trigger- a trigger generator producing triggers on wanted intervals.In real system- trigger injected from outside • Data- 8 dip switches selecting 4 different modes for each channel: 4 frequencies- full, double, 4 times and 8 times the original frequency. 4 phases-In real system- as many bits as wanted from outside

12. Trigger Out Shift Register (size determined by user) TRIG_IN Flip-Flop Flip-Flop TRIG_OUT Flip-Flop … CLK CLK CLK CLK

13. DDS Module3 DDS Module0 DDS Implementaionusing xilinx DDS IP coreDDS BLOCK DIAGRAM CE CE SCLR SCLR SINE[0..SINE_WIDTH-1] SINE[0..SINE_WIDTH-1] WE WE REG_SELECT REG_SELECT PHASE_OUT[0..PHASE_WIDTH-1] PHASE_OUT[0..PHASE_WIDTH-1] DATA[0..PHASE_WIDTH-1] DATA[0..PHASE_WIDTH-1] CE SCLR SINE0 WE REG_SELECT PHASE_OUT0 CONFIG _DATA0 SINE3 PHASE_OUT3 CONFIG _DATA2

14. DDS results- Distributed550 MHz clock, sampled at 550 MHz – on Logic AnalyzerMaximal possible frequency • No noise !

15. DDS results-DistributedTrigger in action • 6 clocks after trigger, the phase resets to 0.

16. DDS results550 MHz clock, sampled at 4 GHz – on Logic Analyzer Significant noise ! Let us focus on one particular “spike”

17. Zoom on “Spike”

18. Zoom on “Spike” • There is a 500ps (at least) long transient : “11010000””11110010” (TransientValue) ”10111010”. • The Tpd of the DDS is longer than 250ps which is the sampling interval, and therefore we see the transient which occurs within the Tpd.

19. DDS results- Blocked550 MHz clock, sampled at 550 MHz –on Logic AnalyzerMaximal possible frequency • No noise !

20. DDS results- BlockedTrigger in action • 6 clocks after trigger, the phase resets to 0.

21. Conclusions • Maximal frequency is : • 550 MHz is the maximal working frequency of Xilinx’s DDS core.

22. Sine generator – Memory implementation 00000 • Addresses jump will be determined by initialized frequency. • Initial address will be determined by initialized phase • Required memory size: 32*word width *4 channelsFor word width=32: 4096 00001 00010 Sine 11110 11111

23. Memory implementation – “Sine Generator” Block Diagram PHASE_OUT ADDRESS RESET ADDR A RESET SCLR SINE SCLR DOUTA CE Address Generator ROM CE PINC CLK POFF CLK A WE PINC REG 0 WE pinc_sig DATA 1 RESET RESET REG SELECT WE DATA poff_sig 0 POFF REG DATA RESET 1 RESET CLK

24. Memory implementation – Address Generator Block Diagram Address Generator RESET ADDRESS CE SCLR RESET WE 1 DATA 0 REGISTER + OUT PINC POFF CLK

25. Option 1- Blocked memory Pros-* dedicated memory blocks on board. * Decreased noise at high frequency - because it is synchronous the critical path is shorter and Tpd is shorter.Cons–* extra cycle delay from trig because of synchronous read

26. Blocked Memory results700 MHz clock, sampled at 700 MHz – on Logic AnalyzorMaximal possible frequency No noise !

27. Delay from trigger • 3 Clocks from trigger, the phase resets

28. Blocked Memory results700 MHz clock, sampled at 4 GHz – on Logic Analyzor Significant noise. Like was explained before, spikes are transients which occurs within the Tpd of the ROM.

29. Block memory Conclusions • Maximal frequency is :

30. Option 2- Distributed memory Pros- * only 2 cycles delay from trig (instead of 3)Cons –* no dedicated blocks, implemented with other components.* Might decrease performance on heavy designs* Noisier at high frequencies – because it is not synchronous the logics’ delay is added to the ROMs’ delay causing higher Tpd.

31. Distributed Memory Results500 MHz clock, sampled at 500 MHz– on Logic Analyser No Noise !

32. Distributed Memory ResultsDelay from trigger • 2 Clocks from trigger, the phase resets

33. Distributed Memory Results700 MHz clock, sampled at 700 MHzMaximal possible frequency Noise exists but is not significant – good enough.

34. Distributed Memory ResultsDelay from trigger 2 Clocks from trigger, the phase resets.

35. Conclusions • Maximal frequency is :

36. Blocked Memory results700 MHz clock – 22 samples per period , sampled at 700 MHz – on Logic Analyzer No Noise !

37. Blocked Memory results700 MHz clock – 22 samples per period - Delay from Trigger 3Clocks from trigger, the phase resets.

38. Conclusions • Maximal frequency is :

39. Prefomance and Utalization comparison (1)

40. Prefomance and Utalization comparison (2)

41. Main Problems encountered • Physical switches noise- the switches produced significant noise interfering with the proper operation of the system. Solution: Debouncer • Chipscope noise- Significant noise was sampled in the chipscope.Solution: Sampling with Logic Analyzer. Chipscope false sampling

42. Future Project Development • Add an interface with an outer system such as PC. • Interfacing with D2A and sampling the analog signal with scope. • Add an analog noise filter to overcome unwanted noise. • Implement and/or use a higher frequency clock, to achieve higher operating frequency.

43. Gantt Chart Mid Term 14/4/2013 Actual Final 9/6/2013 Original Final 1/7/2013

44. Demonstration!

45. Thank you for listening!