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Generating minimum transitivity constraints in P-time for deciding Equality Logic

This paper discusses the generation of minimum transitivity constraints for deciding equality logic in polynomial time, providing an improvement over previous methods. It explores different approaches and their effectiveness, and presents results from experiments and benchmarks.

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Generating minimum transitivity constraints in P-time for deciding Equality Logic

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  1. Generating minimum transitivity constraints in P-time for deciding Equality Logic Ofer Strichman and Mirron Rozanov Technion, Haifa, Israel Technion

  2. Deciding Equality Logic (TE) • The eager approach: TE! Pr • Bryant & Velev [BV-CAV’00] – Boolean satisfiability with transitivity constraints. • Meir and Strichman [MS-CAV’05] – Yet another decision procedure for equality logic. • This work: a ‘closure’ on [MS-CAV’05] Technion

  3. Basic notions E: x = yÆy = zÆzx (non-polar) Equality Graph: y x z Technion

  4. From Equality to Propositional Logic[BV-CAV'00] – the Sparse method x1 E :x1 = x2Æx2 = x3Æx1x3 sk : e1,2 Æe2,3Æ:e1,3 • Encode all edges with Boolean variables • Add transitivity constraints e1,2 e1,3 x2 e2,3 x3 Technion

  5. From Equality to Propositional Logic[BV-CAV'00] – the Sparse method x1 E :x1 = x2Æx2 = x3Æx1x3 sk : e1,2 Æe2,3Æ:e1,3 • Transitivity Constraints: For each cycle of size n, forbid a true assignment to n-1 edges T S = (e1,2Æe2,3!e1,3) Æ (e1,2Æe1,3!e2,3) Æ (e1,3Æe2,3!e1,2) Check: skÆTS e1,2 e1,3 x2 e2,3 x3 Technion

  6. From Equality to Propositional Logic[BV-CAV'00] – the Sparse method • Thm-1: It is sufficient to constrain chord-free simple cycles • There can be an exponential number of chord-free simple cycles… e2 e5 e1 e3 e4 Technion

  7. From Equality to Propositional Logic[BV-CAV'00] – the Sparse method • Make the graph ‘chordal’. • In a chordal graph, it is sufficient to constrain only triangles. • Polynomial # of edges and constraints. • # constraints = 3 £ #triangles Technion

  8. An improvement[MS-CAV’05] – the RTC method • So far we did not consider the polarity of the edges. • Assuming E is in Negation Normal Form E: x = yÆy = zÆzx y (polar) Equality Graph: = = x z  Technion

  9. e3 e1 e2 An improvementReduced Transitivity Constraints (RTC) • Here, T R = e3Æe2!e1 is sufficient • This is only true because of monotonicity of NNF z Allowing e.g. :x = z, x = y, zy F T  ’:x = z, x = y, z = y T = = y x T Technion

  10. Definitions • Dfn-1: A contradictory cycle is a cycle with exactly one disequality edge. • Dfn-2: A contradictory Cycle C is constrainedunder T if T does not allow such an assignment. T T C = T T F  Technion

  11. Main theorem[MS-CAV’05] • LetT Rbe a conjunction of transitivity constraints. • IfT Rconstrains all simple contradictory cycles thenE is satisfiable iff skÆT R is satisfiable The Equality Formula Technion

  12. Transitivity: 5 constraints RTC: 0 constraints T Transitivity: 5 constraints RTC: 1 constraint T T T F Technion

  13. Applying RTC • How can we use the theorem without enumerating contradictory cycles ? • Answer: • Consider the chordal graph. • Still – which triangles ? which constraints? Technion

  14. The RTC solution [MS-CAV’05] • 1) Exp # cycles to traverse 2) Not all cycles are simple. • Solution to 1): Stop before adding an existing constraint • Solution to 2): Explore only simple cycles • These solutions cannot be combined. x2 x0 x4 cache: e0,2 Æe1,2 e0,1 e1,3 Æe2,3 e1,2 e2,4 Æe3,4 e2,3 e0,2 Æe0,4 e2,4 x1 x3 Technion

  15. x7 Constraining simple contradictory cycles • Focus on each solid edge es separately • - (find its dashed Bi-connected component) 2. Make the graph chordal x2 x0 x4 es x1 x5 x3 x6 Do we need: e5,6Æ e3,6! e3,5 ? Do we need: e3,5Æ e3,6! e5,6 ? Technion

  16. Constraining simple contradictory cycles 3.Remove a vertexxkthat leans on an edge(xi,xj) 4.Is(xi,xj)on a simple cycle withes?O(|E|) 5.If yes, add(ek,iÆ ek,j! ei,j) e5,6 Æe3,6 e3,5 x2 x0 x4 es x1 x5 x3 x6 Technion

  17. Constraining simple contradictory cycles • Remove a vertex vkthat leans on an edge (vi,vj) • Does (vi,vj) on the same simple cycle with es? • If yes, add (ek,iÆ ek,j! ei,j) e5,6 Æe3,6 e3,5 x2 x0 x4 es x1 x5 x3 x6 Technion

  18. Correctness • The set of generated constraints is sufficient. • The set of generated constraints is necessary. Technion

  19. Random graphs (Satisfiable)[MS-CAV’05] Technion

  20. Results – random graphs V=200, E=800, 16 random topologies # constraints: reduction of 17% Run time: reduction of 32% Technion

  21. Results – random graphs V=200, E=800, 16 random topologies # constraints: reduction of 17% Run time: reduction of 32% Technion

  22. SMT benchmarks • Never really finished the implementation… • Our 4-5 experiments with them showed that • We still have a small advantage comparing to the Sparse method. • Yet Yices is much better…. • A result of the Uninterpreted functions. • Are there formulas for which the eager approach still wins? • Generating meaningful equality formulas is hard… Technion

  23. A crafted example 2n assignments satisfysk. None satisfy the theory. Technion

  24. Thank you Technion

  25. ResultsUclid benchmarks* (all unsat) * Results strongly depend on the reduction method of Uninterpreted Functions. Technion

  26. Possible refutations of CNF’s generated by Sparse Transitivity constraints Boolean Encoding Æ T S B B T R P3 P2 P0 P4 T S – T R P1 P2 Constraints of the form e1Æ e2! e3 A P3 proof exists according to the main theorem. Hypothesis: (T S – T R) clauses hardly participate in the proof Thm: B is satisfiable !B Æ (T S – T R) is satisfiable Technion

  27. B T R Average on: 10 graphs, ~890K clauses All Unsat Sparse: ~ 22 sec. RTC: ~ 12 Sec. T S- T R B T R B – Boolean encoding T R –RTC constraints T S –Sparse constraints T S- T R Technion

  28. Summary • The RTC method is ~dominant over the Sparse method. • Open issue: find a P-time algorithm that exploits the full power of the main theorem. Technion

  29. Example: Circuit Transformations Stage 1 • A pipeline processes data in stages • Data is processed in parallel – as in an assembly line • Formal Model: Stage 2 Stage 3 Technion

  30. Example: Circuit Transformations • The maximum clock frequency depends on the longest path between two latches • Note that the output of g is usedas input to k • We want to speed up the design by postponing k to the third stage Technion

  31. Validating Circuit Transformations ? = Technion

  32. Source program z= (x1+y1)  (x2+y2); Target program u1=x1+y1;u2=x2+y2;z=u1u2 ; Validating a compilation process Compilation • Need to prove that:(u1=x1+y1 u2=x2+y2  z=u1u2) $z= (x1+y1)  (x2+y2) Source Target Technion

  33. Validating a compilation process • Target program u1=x1+y1;u2=x2+y2;z=u1u2 ; • Source program z= (x1+y1)  (x2+y2); Compilation • Need to prove that:(u1=x1+y1 u2=x2+y2  z=u1u2) $z= (x1+y1)  (x2+y2) g1 f1 f2 f1 f2 g2 Technion

  34. Need to prove that:(u1=x1+y1 u2=x2+y2  z=u1u2) $z= (x1+y1)  (x2+y2) g1 f1 f2 f1 f2 g2 Validating a compilation process • Instead, prove: under functional consistency: for every uninterpreted function fx = y!f(x) = f(y) • Which translates to (via Ackermann’s reduction): Technion

  35. Definitions for the proof… • A Violating cycle under an assignment R: • This assignment violates T S but not necessarily T R Either dashed or solid eT1 F T eF T eT2 Technion

  36. More definitions for the proof… • An edge e = (vi,vj) is equal under an assignment  iff there is an equality path between vi and vj all assigned T under . Denote: v3 T F T v1 v2 T T Technion

  37. More definitions for the proof… • An edge e = (vi,vj) is disequal under an assignment  iff there is a disequality path between vi and vj in which the solid edge is the only one assigned false by . Denote: v3 T F T v1 v2 T T Technion

  38. v3 F T T v1 v2 Proof… • Observation 1:The combinationis impossible if = R(recall:R²T R) • Observation 2: if (v1,v3) is solid, then Technion

  39. Type 1: It is not the case that Assign S (e23) = F Type 2: Otherwise it is not the case that Assign  (e13) = T ReConstructing S v3 v3 F F T  T T  F T T v1 v1 v2 v2 In all other casesS = R Technion

  40. ReConstructing S • Starting from R, repeat until convergence: • (eT) := F in all Type 1 cycles • (eF) := T in all Type 2 cycles • All Type 1 and Type 2 triangles now satisfy T S • B is still satisfied (monotonicity of NNF) • Left to prove: all contradictory cycles are still satisfied Technion

  41. T T Proof… • Invariant: contradictory cycles are not violating throughout the reconstruction. • contradicts the precondition to make this assignment… v3 F T  F T v1 v2 Technion

  42. T F Proof… • Invariant: contradictory cycles are not violating throughout the reconstruction. • contradicts the precondition to make this assignment… v3 F  T T T v1 v2 Technion

  43. Constraining simple contradictory cycles The constraint e3,6 Æe3,5 e5,6is not added cache: … e5,6 Æe4,6 e4,5 x2 x0 x4 x1 x5 x3 x6 Open problem: constrain simple contradictory cycles in P time Technion

  44. Constraining simple contradictory cycles the constraint e3,6 Æe3,5 e5,6is not added, though needed Suppose the graph has 3 more edges Here we will stop, although … cache: … e5,6 Æe4,6 e4,5 x2 x0 x4 x1 x5 x3 x6 Open problem: constrain simple contradictory cycles in P time Technion

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