High-level Synthesis and System Synthesis

1. High-level Synthesis and System Synthesis • Camposano, • J. Hofstede, • Knapp, • MacMillenLin SOURCES- Mark Manwaring Kia Bazargan Giovanni De Micheli Gupta Youn-Long Lin

2. Why the level of automation must go up and up?

3. What Went Wrong with early approaches to design automation ? • Too much emphasis on incremental work on algorithms and point tools • Unrealistic assumption on component capability, architectures, timing, etc • Lack of quality-measurement from the low level • Too many promises on fully automated system (silicon compiler??)

4. Example of a Silicon Compiler System Initial specification

5. Benchmarks for a silicon compiler

6. VLSI Design Tools • Design Capturing/Entry • Analysis and Characterization • Synthesis/Optimization • Physical (Floor planning, Placement, Routing) • Logic (FSM, Retiming, Sizing, DFT) • High Level(RTL, Behavioral) • Management

7. Specify and ??? Describe and Synthesize Design Methodology Progress Capture and Simulate

8. Why not Synthesis? Why Synthesis? Productivity Performance Loss Correctness Unsynthesizability Re-Targetability Inertial

9. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Y-Chart Dan D Gajski Floorplan Physical

10. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Layout Synthesis Floorplan Physical

11. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Logic Synthesis Floorplan Physical

12. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement High-Level Synthesis Floorplan Physical

13. Target Architectures • Bus-based • Multiplexer-based • Register file • Pipelined • RISC, VLIW • Interface Protocol

14. Goal of synthesis for future systems From Behavioral specification at ‘System Level’(Algorithms) To Structural implementation at ‘Register Transfer Level’ of Data path (ALU’s, REG’s, MUX’s) and Controller • Generally restricted to a single process • Generally data path is optimized; controller is by-product

15. In Camposano Behavioral Register-Transfer (RTL) Logic Our Abstraction levels System Register Logic Levels of Abstraction

16. Abstraction levels Level Behavior Structure Synthesisstep System High-level Logic Physical

17. Intermediate Representation * * + Data Flow Graph Control Flow Graph

22. What are possible levels of synthesis? What are possible styles? How to automate big tasks?

24. Layout Synthesis

25. CompassPlacement & Routing ( 0.6µm gate array)

26. Layout Level

27. Logic Synthesis

28. Reminder about blocks and connections in data path

29. Variants of simple FSMD architectures Controlling /activation pulses control Data Path Controlling /activation pulses control Data Path Status signals

30. Variants of simple FSMD architectures Controlling /activation pulses Data Path control Instructions Status signals

31. Interactive FSMDs FSM FSM FSM Data Path Data Path Data Path FSM with Data Path (FSMD)

32. Details of control signals Register; a) RTL level b) with control signal details • controls: • Reg_EO Enable Output • Reg_EI Enable Input • RegFile_EI RegFile_SI <p>

33. Control of register files • control signals: • RegFile_EO1 RegFile_SO1 <p> • RegFile_EO2 RegFile_SO2 <p> • RegFile_EI RegFile_SI <p> Register; a) RTL level b) with control signal details

34. The role of tri-state signals Scheduling and allocation problems are similar Tri-state signals in buses instead of multiplexing

35. Multiplexing

36. Communication with a memory External address-bus External data-bus Internal bus

37. Pipeline Design Issues • Pipelined processor design • Pipeline is an implementation issue. • A behavioral representation should not specify the pipeline. • Most processor instruction sets are conceived with an implementation in mind. • The behavior is defined to fit an implementation model.

38. Semantics of variables • Variables are implemented in hardware by: • Registers. • Wires. • The hardware can store information or not. • Cases: • Combinational circuits. • Sequential circuits.

39. Semantics of variables Semantics of variables • Combinational circuits. • Multiple-assignment to a variable. • Conflict resolution. • Oring. • Last assignment.

40. Semantics of variables Semantics of variables • Sequential circuits. • Multiple-assignment to a variable. • Variable retains its value until reassigned. • Problem: • Variable propagation and observability.

41. Example Semantics of variables • Multiple reassignments: • x= 0 ; x = 1 ; x = 0 ; • Interpretations: • Each assignment takes a cycle. --> pulse. • x assumes value 0. • x assumes value 0 after a short glitch.

42. Timing semantics Semantics of variables • Most procedural HDLs specify a partial orderamong operations. • What is the timing of an operation? • A posteriori model: • Delay annotation. • A priori model: • Timing constraints. • Synthesis policies.

43. Timing semantics(event-driven semantics) • Digital synchronous implementation. • An operation is triggered by some event: • If the inputs to an operation change --> the operation is re-evaluated. • Used by simulators for efficiency reasons.

44. Synthesis policyfor VHDL and Verilog • Operations are synchronized to a clock by using a wait(or @) command. • Waitand @ statements delimit clock boundaries. • Clock is a parameter of the model: • model is updated at each clock cycle.

45. Verilog examplebehavior of sequential logic circuit module DIFFEQ (x, y, u , dx, a, clock, start); input [7:0] a, dx; inout [7:0] x, y, u; input clock, start; reg [7:0] xl, ul, yl; always begin wait ( start); while ( x < a ) begin xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + (u * dx); @(posedge clock); x = xl; u = ul ; y = yl; end endmodule

46. Abstract models • Models based on graphs. • Useful for: • Machine-level processing. • Reasoning about properties. • Derived from language models by compilation.

47. Abstract modelsExamples • Netlists: • Structural views. • Logic networks • Mixed structural/behavioral views. • State diagrams • Behavioral views of sequential logic models. • Dataflow and sequencing graphs. • Abstraction of behavioral models.

48. Data flow graphs • Behavioral views of architectural models. • Useful to represent data-paths. • Graph: • Vertices = operations. • Edges = dependencies.

49. Dataflow graph Example xl = x + dx ul = u - (3 * x * u * dx) - (3 * y * dx) yl = y + u * dx c = xl < a

50. Example of Data Flow Graph continued xl = x + dx ul = u - (3 * x * u * dx) - (3 * y * dx) yl = y + u * dx c = xl < a