Finding the Minimal Logic Difference for Functional ECO

2012 CAD Contest Finding the Minimal Logic Difference for Functional ECO Black Yu, Charlotte Lin, Jerry Wang, and Randy Chen

Outline • Problem • Flow • Studies • Future Work

Problem o1 o1 • Given g2 g2 n3 g4 n2 n2 n1 g1 g1 g3 x1 x2 x1 x2 x3 x3 <g1.v> <g2.v>

Problem o1 o1 patch.v • Find g2 g2 n3 g3.v g4 n2 n2 n1 g1 g1 g3 x1 x2 x1 x2 x3 x3 <g1.v> <g2.v>

Flow Old Circuit Golden Circuit Verilog Parser Verilog Parser Difference Identification Patch Construction Patch Minimization Patch Patched Circuit

Studies • Interpolation-based: A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques (2010) Interpolation-Based Incremental ECO Synthesis for Multi-Error Logic Rectification (2011) • Matching-beased: DeltaSyn: An Efficient Logic Difference Optimization for ECO Synthesis (2009) Match and Replace – A Functional ECO Engine for Multi-Error Circuit Rectification (2011)

Future Work • Implementation: • Studies: Difference Identification Patch Construction

Finding the Minimal Logic Difference for Functional ECO