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Finding the Minimal Logic Difference for Functional ECO

2012 CAD Contest. Finding the Minimal Logic Difference for Functional ECO. Black Yu , Charlotte Lin, Jerry Wang, and Randy Chen. 2012 CAD Contest. Outline. Problem Formulation Flow Current Progress Problems & Solutions SAT-based diagnosis Craig interpolation Node merging

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Finding the Minimal Logic Difference for Functional ECO

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  1. 2012 CAD Contest Finding the Minimal Logic Difference for Functional ECO Black Yu, Charlotte Lin, Jerry Wang, and Randy Chen

  2. 2012 CAD Contest Outline • Problem Formulation • Flow • CurrentProgress • Problems & Solutions • SAT-based diagnosis • Craig interpolation • Node merging • Experimental Result

  3. 2012 CAD Contest ProblemFormulation o1 o1 • Given g2 g2 n3 g4 n2 n2 n1 g1 g1 g3 x1 x2 x1 x2 x3 x3 <g1.v> <g2.v>

  4. 2012 CAD Contest Problem Formulation o1 o1 patch.v • Find g2 g2 n3 g3.v g4 n2 n2 n1 g1 g1 g3 x1 x2 x1 x2 x3 x3 <g1.v> <g2.v>

  5. 2012 CAD Contest Flow Old Circuit Golden Circuit Verilog Parser Difference Identification Patch Construction Patch Minimization Patch Patched Circuit

  6. 2012 CAD Contest Current Progress

  7. 2012 CAD Contest SAT-based Diagnosis • Input: A set of candidate signals • Output: A set of feasible rectification points • Problem: Consuming so much time • Solution: • Counterexample covering: (𝑟1+𝑟2)(𝑟3)(𝑟2+𝑟3)(𝑟1+𝑟2+𝑟3) • Cardinality constraints • Reducing candidates (fail) • More heuristics ?

  8. P • Pioff Pion • 2012 CAD Contest Craig Interpolation • Input: Pion and Pioff • Output: Interpolantof Pion and Pioff • Problem: The generated patch is too large • Solution: Extracting minimum UNSAT core (MUC). ITP (Pion, Pioff)

  9. 2012 CAD Contest Node Merging • Input: Patch nodes and g1 • Output: Minimized patch • Status: Integrating…

  10. 2012 CAD Contest Experimental Result

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