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@HDL Presentation for OCP-IP Functional Verification Working Group 3 June 04

@HDL Presentation for OCP-IP Functional Verification Working Group 3 June 04. www.atHDL.com. Agenda. @HDL Company Overview Product Family Details @HDL Collaboration with FVWG Details of Deployment and Support Model Question and Answer Session Action Item Summary.

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@HDL Presentation for OCP-IP Functional Verification Working Group 3 June 04

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  1. @HDL Presentation for OCP-IP Functional Verification Working Group3 June 04 www.atHDL.com

  2. Agenda • @HDL Company Overview • Product Family Details • @HDL Collaboration with FVWG • Details of Deployment and Support Model • Question and Answer Session • Action Item Summary

  3. Based in Milpitas, California, founded in 1999 • Since 2001, delivering innovative software solutions which • significantly improve functional verification productivity • @Verifier and @Designer products uniquely provide • support for Assertion-based Verification • Accellera PSL Sugar • SystemVerilog Assertions (SVA) • Customers include leading semiconductor and • networking / communications companies in US and Japan • New Product Introductions in 2H/2003 • @Verifier-ZX • @Designer-PRO with patent-pending Assertion Studio technology • PSL Engine

  4. RTL Assertion Test bench Find Bugs Faster Simulation Locate Bugs Faster @HDL Products

  5. Some companies using our products

  6. @HDL Version 4.0 Product Families DP ZX Finds the toughest design problemsby innovative application of Formal Model Checking and Clock Domain Analysis, Supporting PSL, OVA and SystemVerilogAssertions Delivers a next generation graphical debugging and design analysis environment to quickly isolate functional errors during creation, model checking, simulation, assertion development and test bench debugging PRO

  7. @HDL Functional Verification Flow Verilog RTL with embedded assertions PRO User-written PSL & SystemVerilog developed with Assertion StudioTM DRC and Formal DRC Constraints Formal Model Checking Fix Design Automatically Generated Assertions Fix Assertions, Add Constraints Failing Assertions Graphical Debugger

  8. Verification Flow using an ABV Methodology Specification – Protocols, Interfacing, etc. Development Verification Assertion Debug Coverage

  9. Assertion Browser Functional Coverage Assertion Debug Failure Waveforms Formal Verification and Analysis

  10. Waveform DB / VCD STEP 2 • Verifying correct • behavior of assertions • without simulating • Modifying and • Testing faulty assertions Interpreter STEP 1 STEP 3 Timing Diagrams PSL User Written Verification Visualizer SVA Formal Engines Sim Engines • Pass / Fail • @HDL PSL Engine for Sim • @Verifier, DP, ZX for Formal Assessor STEP 5 Explorer • Statistical Analysis • Regression Analysis STEP 4 • Detailed assertion execution analysis • Tracing the causes of failing/passing assertions • Use Interpreter for modified assertions Assertion StudioTM Technology [ Patent-pending ] @HDL Assertion Studio Unified Simulation & Formal ABV

  11. @HDL Assertion StudioTMKey Components • Timing Diagrams from PSL & SV Assertions • Interactive Verification of PSL and SVA • PSL Engine for use with non-PSL simulators • Assertion Debugging • Transaction Display and Debugging • Assertion Coverage Reporting from Simulation

  12. Visualizer • Automatically convert user-written assertions into • Timing Diagrams • Key Benefits: • Rapid learning of assertion language • Documentation for RTL blocks with Assertions • Ability to look at 3RD party IP • Avoid multiple iterations of costly formal / simulation cycle ASSERTION STUDIO

  13. Interpreter • Verifies the assertions based on waveform dump (VCD) • without running simulation or formal… • Key Benefits: • Early verification of assertions before actual deployment in • regression test suites • Users can add assertions and verify / debug against the VCD • Avoid multiple iterations of time-consuming formal & simulation • Users can rapidly iterate on assertion code and validate ASSERTION STUDIO

  14. Delivering industry-leading ABV products, addressing the key areas of usability, performance and capacity • Key Benefits – Formal Engine: • Best in class formal solvers (@HDL and IBM Rulebase) • Distributed Processing • Incremental and Hierarchical • Selective Deep-Formal • PSL and OVA/SVA Support • Automatic Assertion Extraction • Multiple Clock Domain Verification ASSERTION STUDIO

  15. Model Checking Algorithms • BDD Based with full model checking • Explores the complete space • Complete proof guaranteeing both pass and fail • SAT based algorithms • Bounded model checking. • Checks for specified number of cycles from current state • Advanced algorithms based on trajectory and path evaluations

  16. ZX • IBM RuleBase solvers • Advanced Formal Algorithms • BDD + SAT • IBM Search Heuristics • Logic reductions • ____________________ • Superior Performance • Large Capacity • Used Extensively inside IBM • Automatic Property Extraction • Clock Domain Properties • FSM deadlock assertions • ….. • Advanced Usability Solutions • Hierarchical, Incremental • Distributed • Selective Deep-formal • Integrated RTL debugging @HDL IBM +

  17. Explorer • Temporal decomposition of the assertion into • sub-expressions to assist in precisely isolating the failing • portion of the assertion • Key Benefits: • Rapid isolation of the failure • Easy to use and debug • Common Debugging Environment covering Formal and Simulation ABV ASSERTION STUDIO

  18. Assessor • Allows users to perform coverage analysis for assertions, as • well as transactions • Key Benefits: • Assertion coverage • Utilize same language to determine transaction coverage • Provides detailed view when the assertion was covered during simulation • Creates a functional coverage matrix • Same language used to do temporal search while debugging ASSERTION STUDIO

  19. PRO //psl property request = always {req & ~busy;busy;gnt & busy;busy;busy;~gnt & ~busy}; //psl assert request;

  20. DP Distributed Processing Support • Main Allocation Algorithms based on clustering of properties for the same cone of influence • Automatically Allocate property checking across network resources using load sharing software • Results in close to linear speed-up

  21. Assertion StudioTM Model Checking Debug SV Testbench Language Debugging Clock Analysis, Visualization PRO Find more bugs, faster. SystemVerilog Source Code Browser Static Analysis Timing and Hotspot Analysis Waveform Debugging

  22. Tooltip Popup Shows Domain Clock Domain Analysis PRO Clock Domain Colorization Enabled Error Messages Linked to Source

  23. Graphically Debug: • Insufficient Synchronization • Multidomain Combinational Logic • Combinational Synchronizer Inputs • Color-coded Verilog Source • Color-coded Schematic • Generate Assertions: • Data Stability • FIFO Read/Write Pointers • Check Assertions: • @Verifer Model Checking • Write out for simulation @HDL Clock Domain Analysis Verilog RTL + Info File

  24. SystemVerilog Support with @HDL Design Testbench Assertions Q2/04 n / a Q1/04 PRO Q2/04 Q3/04 Q1/04

  25. SystemVerilog Assertion Unified Assertion-based Functional Verification Formal, Simulation and Debugging Automatic Assertion Extraction PSL Assertion RTL Assertions for SoC Design Model Checking Debugging @HDL Simlink Direct Link Simulation

  26. Version 4.0 Release of @Verifier @Verifier 4.0 Standard Package includes: PSL and SystemVerilog Support for Model Checking Automatic and User-written Assertions 1 copy of @Designer-PRO 1 copy of PSL Simlink Engine with Run-time license Options with additional license fees for: - Multiple Clock Domain Verification and Analysis - DP Distributed Processing for 4CPU and 8CPU - ZX with IBM RuleBase Solvers - DCS for use with PSL or SVA - PSL Simlink Engine Run-time tokens (10-pack and 25-pack)

  27. Version 4.0 Release of @Designer @Designer-PRO - Integrated Graphical Debugging for both simulation and Assertion-based verification - Adds Assertion StudioTMTechnology - Supports both PSL and SV development and debugging for design, assertions and testbench @Designer - Integrated Graphical Debugging for both simulation and Assertion-based verification - Supports both PSL and SVA assertion debugging

  28. @HDL Collaboration ModelABV “Fast-Track” • Assertion-based Verification Methods “Fast-Track” • Accelerate ABV learning curve with free, limited time • access to @Designer-PRO for OCP-IP members • “Fast Track” participants working on developing • PSL and/or SystemVerilog assertions for OCP-IP • Quantity and duration of “free” licenses to be determined • @HDL provides technical documentation and • training material, tailored towards OCP-IP designs • @HDL allowed to prospect the Fast Track users for • follow-on license sales

  29. “Fast Track” Collaboration Plan • Fill-in the details, restrictions, limitations • Announce the @HDL / OCP-IP Alliance • Deploy @Designer-PRO to the community • Extend training and specialized support services with complementary DV services companies • Promote availability of PSL/SV assertions for validation of OCP-IP designs… - seminars, articles…

  30. Concluding Items • Discuss Fast Track details • Open Q&A • Action Item Summary

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