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Some Data Rate Issues in the L1 Trigger System

Some Data Rate Issues in the L1 Trigger System. July 2004. Outline. Capacities of data flow at the connection ports. Relative data rate evolution in each stage. Pixel Data. L1 Block Diagram. Time Stamp Ordering. TSO. TSO. TSO. TSO. TSO. TSO. TSO. TSO. TSO. TSO. TSO. TSO.

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Some Data Rate Issues in the L1 Trigger System

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  1. Some Data Rate Issues in the L1 Trigger System July 2004

  2. Outline • Capacities of data flow at the connection ports. • Relative data rate evolution in each stage.

  3. Pixel Data L1 Block Diagram Time Stamp Ordering TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO Raw Data to L1B Cluster Processing Triplets to L1B PP PP PP PP PP PP PP PP PP PP PP PP Data Sharing ST ST ST ST ST ST ST ST ST ST ST ST L1B Segment Finding L1B Servers L1 Switch Event Building Tracks & Vertices to L1B BM BM BM BM BM BM BM BM L1B Track & Vertex Processing CPU CPU CPU CPU CPU CPU CPU CPU L1B Servers GL1 Node Trigger primitives to GL1

  4. TSO TSO TSO TSO PP PP PP PP ST/L1B ST ST ST/L1B ST/L1B ST ST/L1B ST ST/L1B ST ST ST/L1B ST/L1B ST ST ST/L1B Gang Things Together & Reroute Cables TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO TSO Events are built during TSO & PP processing. L1B for raw data, triplets & etc. PP PP PP PP PP PP PP PP PP PP PP PP Triple links are not needed. ST ST ST ST ST ST ST ST ST ST ST ST L1B L1B Servers L1 Switch BM BM BM BM BM BM BM BM L1B L1 Switch is gone, its functions are absorbed in TSO & PP stages. CPU CPU CPU CPU CPU CPU CPU CPU L1B Servers GL1 Node

  5. 16 10 64 32 16 32 System Interconnection (1 Hwy) Time Stamp Ordering Module Segment Tracker & L1B Module L1B Server PC Pixel Pre-processor Module Buffer Manager Module Worker Farm Node

  6. SRAM-ZBT 128K x 32 SRAM-ZBT 128K x 32 SRAM-ZBT 128K x 32 SRAM-ZBT 128K x 32 SDRAM GL1 Interface SRAM-ZBT 128K x 32 SDRAM SDRAM SDRAM SDRAM ST 2-in 2-out ST 2-in 2-out ST 2-in 2-out ST 2-in 2-out L1B Logic L1B Logic L1B Logic L1B Logic SRAM-ZBT 128K x 32 SRAM-ZBT 128K x 32 SDRAM SDRAM BM Hash Sorter BM Hash Sorter A possible GL1 Interconnection (3) The same BM module is used as GL1 interface. GL1 Node ST/L1B (2) The TSO modules can be used as concentrators. (1) GL1 are sent out by the Worker Nodes. Farm Nodes

  7. Throughput Capacities

  8. Relative Data Volume Evolution in Different Stages • When the data are repackaged (such as in PDCB), data rate may be reduced. • When the data are reordered (such as in Time Stamp Ordering Module), data rate may be reduced. • When the data are duplicated (such as in Pixel Pre-processor Module), data rate will increase.

  9. X X X 0 0 Invalid coding: 1 0 1 1 X Sync24 Status 000 1 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 DW0: Module # Row Column DW1: BCO(11:3) ADC0 Chip # Optional Continue Word: Hits ADC3 ADC2 ADC1 BCO(2:0) 0 0 Input & Output of PDCB b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Hit24 Row Column BCO(7:0) ADC 1 DCC et al 12.3 Ghits/s x 24 b/hit = 0.3 Tbps (total), 37.5 Gbps/hwy Doc 3233 Doc 2621 12.3 Ghits/s /(2.5 hits/group)x 48 b/group = 236 Gbps (total), 29.5 Gbps/hwy

  10. Idle Words: Status etc. 1 0 1 1 X 00 Status etc. 1 0 1 1 X Idling, an Important Operation b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 DW0: Module # Row Column DW1: BCO(11:3) ADC0 Chip # Optional Continue Word: Hits ADC3 ADC2 ADC1 BCO(2:0) 0 0

  11. BCO(9:0) 1 0 1 1 X Idle Words: BCO(21:9) 1 0 0 00 Status etc. 1 0 0 DW0: Module # Row Column DW1: Hits ADC2 ADC1 ADC0 Chip # NS CW: Hits ADC6 ADC5 ADC4 ADC3 0 0 1 Station 0 0 0 Module # Row Column BCO0 Station 1 1 BCO(11:3) ADC0 Chip # 0 Station 2 Hits ADC3 ADC2 1 ADC1 BCO(2:0) 0 0 Station 0 BCO0+1 1 0 Output of Time Stamp Ordering Module b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Hits: 12.3 Ghits/s /(2.5 hits/group)x 32 b/group = 157 Gbps (total), 19.7 Gbps/hwy

  12. BCO(9:0) 1 0 1 1 X Idle Words: BCO(21:9) 1 0 0 00 Status etc. 1 0 0 DW0: Module # Row Column Same Column CW: DW1: Hits ADC5 ADC4 ADC3 0 0 Hits ADC2 ADC1 ADC0 Chip # NS Cross Column CW: Separator Word: Hits ADC5 ADC4 ADC3 Del Row2 1 0 Separator Type 1 0 1 1 X y0x(8:5) x0x(12:9) NS 1 XY Words: y0x or x0y(4:0) x0x or y0y(8:0) V 0 Additional XY Words: y1x or x1y(4:0) x1x or y1y(8:0) V 0 Output of Pixel Pre-processor Module b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Raw Hits: 12.3 Ghits/s /(2.5 hits/cluster)x 32 b/cluster = 157 Gbps (total), 19.7 Gbps/hwy XY: 12.3 Ghits/s /(2.5 hits/group)x (32+16)b/(2 groups) = 118 Gbps (total), 14.7 Gbps/hwy

  13. Data Rates

  14. Conclusion: • We have large safety factors.

  15. I/O of Time Stamp Ordering Module b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 DW0: Chip # Row Column DW1: BCO(11:3) ADC0 Module # Optional Continue Word: BCO(2:0) ADC3 ADC2 ADC1 Hits 0 0 Idle Words: Status etc. 1 0 1 1 X 00 Status etc. 1 0 1 1 X b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 BCO(7:0) Station # 0 0 Header Long Word: BCO(23:7) Chip # Row Column Hits Long Word: ADC2 ADC1 ADC0 Hits Module # Idle Long Words:

  16. b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 BCO(7:0) Station # 0 0 Header Long Word: BCO(23:7) Chip # Row Column Hits Long Word: NX ADC2 ADC1 ADC0 Hits Module # I/O of Time Stamp Ordering Module b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 DW0: Chip # Row Column DW1: BCO(11:3) ADC0 Module # Optional Continue Word: BCO(2:0) ADC3 ADC2 ADC1 Hits 0 0 Hits: 12.3 Ghits/s /(2.5 hits/group)x 32 b/group = 157 Gbps (total), 19.7 Gbps/hwy Headers (1/hwy): 7.6 MBOC/s x (1/8hwy) x 32b/BCO/port x 480 ports = 14.6 Gbps/hwy

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