Advanced Digital Circuits ECET 146 Week 8

1. Advanced Digital CircuitsECET 146Week 8 Professor Iskandar Hack ET 221B, 481-5733 hack@ipfw.edu

2. This Week’s Goals • Further discussion regarding FSM’s • Modifying an existing design

3. Review of Basic FSM Format Clock State Transition Logic Combination Logic only For decoding State for outputs System Outputs Reset Current State Other inputs

4. Example from Last week Clock State Transition Logic Combination Logic only For decoding State for outputs R Y G North-South Lights Reset Current State te R Y G East-West Lights Start Nsec[3..0]

5. Use of the Table Command for State Transition Logic • The simplest approach designing the FSM state transition logic is use a table with the inputs on the left side of the table along with the state. • The right side of the table will only contain the next state of the FSM. • Remember that a FSM will only change state only on a rising clock edge

6. Example FSM Transition Logic Clock State Transition Logic Reset te

7. Using a Process and Case Statement to control State/Next State Process(clk) Begin if clk'Event and clk = '1' Then Case state IS When s0 => state <= s0a; When s0a => if te = '1' then state <= s1; else state <= s0a; end if; When s1 => state <= s1a; When s1a => if te = '1' then state <= s2; else state <= s1a; end if; When s2 => state <= s2a; When s2a => if te = '1' then state <= s0; else state <= s2a; end if; End Case; End if; End Process;

8. Output Logic Combination Logic only For decoding State for outputs R Y G North-South Lights R Y G East-West Lights Start Nsec[3..0]

9. Logic to control Outputs Based on State With state Select lights <= "100001" When s0, "100001" When s0a, "100010" When s1, "100010" When s1a, "100100" When s2, "100100" When s2a; With state Select nsec <= x"4" When s0, x"4" When s0a, x"8" When s1, x"8" When s1a, x"2" When s2, x"2" When s2a;

10. Multiple Paths in FSM • Thus far all of our FSM’s have been relatively simple in that we either stay in the current state or move to the next state. • However most FSM’s are more complex than that, in that it is possible to easily to move from one state to just one other state, but to one of many other states.

11. Multiple Path Bubble Graph FSM can move from STATE4 to either State6 or State5 depending on the Value of sensor

12. Hint • When you draw the Bubble graph for a FSM design count the number of paths leaving a bubble (a loop back counts as a path). The number of paths for a particular state will equal the options in the VHDL Case statement for that state.

13. Counting paths Two paths leaving State4 Two paths leaving State3 Two paths leaving State5 Two paths leaving State6 Total of eight paths (not counting reset) thus eight lines in Table

14. Midterm Project Stoplight with turn lane sensors 1. Copy all of the files from Lab 7 into a new directory with a new name. 2. Modify the stoplight state machine to include the following new inputs/outputs. a. EWLTS - Left turn switch on E-W (assume only one input for both sides) b. NSLTS - Left turn switch on N-S (assume only one input for both sides) c. EMGS – Emergency Mode Activation Switch d. Expand NSLights to include a LT Green (assume that the LT Green and normal Yellow is lit for the NSLTY states (same for EWLights) 3. Add the following MAJOR states to the state machine from Lab 7. NSLTG 10 secs NSLTY 5 secs EWLTG 10 secs EWLTY 5 secs Determine where these should fall in the overall state machine, and add them. Note you should only enter NSLTG if the input NSLTS is active, and the same with EWLTG. 4. Add an Emergency Mode to the design. In this mode both the NS and EW lights will flash RED and YELLOW. Assume there is another input EMG (single bit-active low) that activates this mode. Set the flash rate as 1 clock cycle on and 1 clock cycle off. 5. Simulate the complete design. 6. Check out from the lab tech an Altera Educational Board, and verify your design.