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P ulse S tart L aser S ynchro

100ms. FSL. n x FSL. QSL. n x QSL. Δ T. 230µs. FML. QML. 140µs. P ulse S tart L aser S ynchro. LabVIEW & F ield P rogrammable G ate A rray. MC68HC08. LabVIEW. USB/VPC. XILINX 255 cycles FSL 1µs < Δ T < 1s Précision = 1µs. FT232. DS1023-500 16,5 à 1292ns. ABEL. VHDL.

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P ulse S tart L aser S ynchro

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  1. 100ms FSL n x FSL QSL n x QSL ΔT 230µs FML QML 140µs PulseStartLaserSynchro LabVIEW & FieldProgrammableGateArray MC68HC08 LabVIEW USB/VPC XILINX 255 cycles FSL 1µs < ΔT < 1s Précision = 1µs FT232 DS1023-500 16,5 à 1292ns

  2. ABEL VHDL XABEL Very High Speed Integrated Circuit Hardware Description Language Advanced Boolean Expression Language Xilinx ABEL réseau de portes programmables in-situ >>>>>>>>> SPARTAN 3E <<<<<<<< — 500 000 Portes —232 E/S réseau de portes programmables in-situ >>>>>>>>> XCS30XL <<<<<<<<<< — 30 000 Portes —192 E/S Logique Programmable Haute-Densité >>>>>>> ISPLSI1032EA <<<<<<< — 6 000 portes — 64 E/S, 4 Entrées dédiées Logique Programmable Haute-Densité >>>>>>> ISPLSI1016E <<<<<<<< — 2 000 portes — 32 E/S, 4 Entrées dédiées CPLD&FPGA Historique LATTICE (CPLD) XILINX (FPGA) Portes Logiques 500 000 30 000 2 000 1998 2007

  3. Xilinx – Présentation Langage ABEL OPERATEURS STRUCTURE MODULEportes "Inputs A, B pin; "Outputs Y1,Y2,Y3,Y4,Y5,Y6,Y7 pin istype 'com'; out = [Y1..Y7]; Equations Y1 = A & B; "Et Y2 = A # B; "Ou Y3 = A $ B; "Ou Exclusif Y4 = !A; "Non Y5 = !(A & B); "Non et Y6 = !(A # B); "Non ou Y7 = !(A $ B); "Non ou Exclusif Test_vectors ([A,B] -> [out]) [0,0] -> [.X.]; [0,1] -> [.X.]; [1,0] -> [.X.]; [1,1] -> [.X.]; END Déclarations • Entrées/Sorties • Nœuds internes Equations • Sortie.__ = Opérations ; • Nœuds.__ = Opérations ; Simulation • test_vectors • trace_statement

  4. Xilinx - Déclarations Vue d’ensemble Entrées Horloge 8 MHz ______________ CLK RAZ du Xilinx _____________ RESET Ordre de lancement ________ START Bus de Donnée ________ HC08[7..0] Bus d’adresse __________ ADR[4..0] Ecriture ____________________ WR Sorties Etat _____________________ BUSY Impulsions _____________ FSL, QSL Impulsions _____________ FML, QML Nœuds Internes / Registres Période ______________ PER[7..0] Registre ΔT ___________ ADR[16.0] Polarité _____________ FSL ... QML Largeur des impulsions _ FSL … QML Compteurs ___________ FSL_à_QSL Compteurs ___________ FML_à_QML

  5. 100ms FSL n x FSL QSL n x QSL ΔT 230µs FML QML 140µs Xilinx - Fonctionnement

  6. Simulation Fonctionnelle

  7. 100ms FSL n x FSL QSL n x QSL ΔT 230µs FML QML 140µs LabVIEW – National Instrument ™ USB: Virtual Port Com n x FSL: Période (ms) ΔT: Delta T(µs)+Delta T (ns) n x QSL: Répétition Polarité: FSL,QSL,FML,QML

  8. LabVIEW – National Instrument ™

  9. Interface de commande LABVIEW d'un microscope

  10. 5ème Rencontre Régionale MERCI

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