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Coincidence Detector on SOPC Final Presentation

Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab. Coincidence Detector on SOPC Final Presentation. Presenting: Roee Bar & Gabi Klein Instructor: Ina Rivkin. Agenda. Project Goals Implementation Method Algorithm

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Coincidence Detector on SOPC Final Presentation

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  1. Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Coincidence Detectoron SOPCFinal Presentation Presenting: Roee Bar & Gabi Klein Instructor: Ina Rivkin

  2. Agenda • Project Goals • Implementation Method • Algorithm • Technical Details • Implementation Limitations • DCM Capabilities • System Description • Results • Achievements • Future Developments Final Presentation

  3. Goals Main Goal: Detect two simultaneous events Additional Goals: • Create a Signal Generator, which will be used to test the detector. • Thoroughly understand the features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro. Final Presentation

  4. Implementation Method • The detector and the generator will be implemented on the Virtex II Pro platform, using the Xilinx XUPV2P Development Board. • The detector unit will detect coincidence of two events in a given timeframe. Final Presentation

  5. T Reminder • In reality, the probability of the two events occurring exactly at the same time is practically zero. Therefore, we have to define a timeframe T. • Two events occurring in this timeframe, are called coincident events. Final Presentation

  6. Algorithm • Let’s examine a coincidence between two signals: A B A XOR B W • Declare coincidence if W<T. • Target: Find out if W<T. Final Presentation

  7. SRFF CLOCK SRFF A XOR B CLOCK’ S S Q Q Clk Clk Algorithm • Let’s examine the following circuit, where the clock cycle is T: A AND B 2: W>T/2 1: 0<W<T 0: W<T/2 Counts the number of ‘1’ F 0 ‘2’ 1 • We assume that if coincidence occurred W<T/2 else W>T. • If F<2 we declare coincidence. Final Presentation

  8. Algorithm • We can improve resolution and detect W<2T/N. • Let’s take N phase shifted clocks where the k-th clock is shifted by kT/N • Then, we’ll connect all the SRFF outputs to a counter. Final Presentation

  9. S S S S Q Q Q Q ClkN Clk1 Clk2 Clk3 Algorithm Counts the Number of ‘1’ inputs In1 In2 F In3 S F=k<N → (k-1)T/N<W<(k+1)T/N F=N → W>(N-1)T/N ‘N’ A XOR B InN A AND B With the result of F, we can determine the signal pulse width range in resolution of 2T/N. Final Presentation

  10. Technical Details • System clock frequency: 100MHz. • We will use DCM to double the clock frequency to 200Mhz. • DCMs used for implementation – 3 • Each DCM has 4 outputs, 4 evenly shifted clocks, which gives us total of 12 shifted clocks. • This gives ability to determine signal pulse width in resolution of 2T/N=832pSec. Final Presentation

  11. Implementation Limitations • In practice the coincidence detects correctly when W<T-d or W>T+d. When T-d<W<T+d the detector output is not defined. In our case: d=417ps, T=5ns. • In our implementation we do not report the pulse length but only report coincidence when W<T-d, or no-coincidence when W>T+d. • After each coincidence the signals should be stable for 2 clock cycles (~20nSec). • Due to flip-flops metastability some signals might not be detected correctly. Final Presentation

  12. DCM Capabilities • The main capability of a DCM is clock de-skewing. • Phase Shifting: Each DCM is capable of driving the input clock in 4 different clock phases, separated by 90° each. • Frequency Synthesis: Input frequency multiplied by two, divided by an integer between 2 and 16, multiplied by M, divided by D. By using these methods, we are capable to create almost any frequency between 3MHz and 420 MHz. Final Presentation

  13. Detector Controller Mini Detection Blocks with DCM • The Detector unit consists of 3 Mini Detection blocks and a Controller Final Presentation

  14. Detector Mini Detection Block DCM • Each Mini Detection block consists of 4 SRFF which handle 4 timeframes. SRFF SRFF SRFF SRFF Final Presentation

  15. Signal Generator • The Signal Generator produces tests signals for the Detector. • Each test consists of two time shifted signals. Final Presentation

  16. Signal Generator Controller DCM DCM Latch Latch Final Presentation

  17. Results • When A XOR B pulse is detected by all detectors – there is no coincidence (Detected output is low). Final Presentation

  18. Results • When A XOR B pulse is not detected by all detectors – there is a coincidence (Detected output is high). Final Presentation

  19. Achievements • Studied ISE, ChipScope, HDL Designer, Precision and ModelSim. • DCM configuration and usage. • Developed a method to detect coincidence using digital components only. • Implemented a Signal Generator to test our Coincidence Detector. Final Presentation

  20. Future Development • When reporting a coincidence, also report the estimated pulse width. • Improving the Coincidence Detector precision by using higher clock frequency or using more DCM units. • Overcome the system metastability issue. Final Presentation

  21. Thanks to the High SpeedDigital System Laboratory Final Presentation

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