The Xilinx 95108 CPLD

1. The Xilinx 95108 CPLD Lecture 4.2

2. 3 In-System Programming Controller JTAG Controller JTAG Port Function Block1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Function Block 3 Global Clocks 3 Global Set/Reset 1 Function Block 4 Global Tri-States 2 or 4 XC9500 CPLDs • 5 volt in-system programmable (ISP) CPLDs • 5 ns pin-to-pin • 36 to 288 macrocells (6400 gates) • Industry’s best pin-locking architecture • 10,000 program/erase cycles • Complete IEEE 1149.1 JTAG capability

3. Global Clocks Global Tri-State 2 or 4 3 I/O Macrocell 1 Product- Term Allocator AND Array 36 From FastCONNECT I/O Macrocell 18 To FastCONNECT XC9500 Function Block Each function block is like a 36V18 !

4. XC9500 Product Family 9536 9572 95108 95144 95216 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 10 Registers 36 72 108 144 216 288 Max I/O 34 72 108 133 166 192 VQ44 PC44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 Packages HQ208 BG352 PQ160 HQ208 BG352

5. Xilinx 95108 • 6 function blocks • Each contains 18 macro cells • Each macro cell behaves like a GAL32V18 • AND-OR array for sum-of-products • 32 inputs and 18 outputs

6. Architecture of the Xilinx XC95108 CPLD

7. PLDT-3 Buttons Xilinx XC95108 CPLD 7 segment display Switches LEDs

8. PLDT-3 • 12 macro cells connected to I/O pins • 4 pushbuttons • 8 toggle switches • 8 dip switches • 16 LEDs • 2 7-segment displays • On-board clock signals (4 MHz and 1 Hz)

9. Designing a Digital Circuit

10. ABEL Advanced Boolean Expression Language An Example

11. ABEL The source file gates.abl