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Asynchronous Interface Specification, Analysis and Synthesis

Asynchronous Interface Specification, Analysis and Synthesis. J. Cortadella Technical University of Catalonia. M. Kishinevsky Intel Corporation. Steps in Design Flow. Specification Synthesis Next-state functions State encoding Decomposition and technology mapping Timing optimization

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Asynchronous Interface Specification, Analysis and Synthesis

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  1. Asynchronous Interface Specification, Analysisand Synthesis J. Cortadella Technical University of Catalonia M. Kishinevsky Intel Corporation

  2. Steps in Design Flow • Specification • Synthesis • Next-state functions • State encoding • Decomposition and technology mapping • Timing optimization • Verification

  3. x y z z+ x- x+ y+ z- y- Signal Transition Graph (STG)

  4. x y z z+ x- x+ y+ z- y-

  5. xyz 000 x+ 100 y+ z+ z+ x- 110 101 x- x+ y+ z- y- y+ z+ 001 111 y- y+ x- 011 z- 010

  6. xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Next-state functions

  7. Next-state functions x y z

  8. Bus Data Transceiver DSr LDS Device D LDTACK DSr LDS VME Bus Controller DSw LDTACK D DTACK DTACK Read Cycle VME bus

  9. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS-

  10. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles

  11. Choice: Read and Write cycles DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw-

  12. Speed independence • Delay model: • Unbounded gate delays • Wire delays after fork are less than gate delays • Conditions for implementability: • Consistent and Complete State Coding • Determinism • Output persistency • Commutativity

  13. State Graph (Read cycle) DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  14. LDS + LDS = 0 LDS - LDS = 1 Binary encoding of signals DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  15. 01100 00110 Binary encoding of signals 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D)

  16. ER (LDS+) LDS+ QR (LDS-) LDS- LDS- LDS- ER (LDS-) QR (LDS+) Excitation / Quiescent Regions

  17. LDS+ LDS- LDS- LDS- Next-state function 0  1 0  0 1  1 1  0

  18. DTACK DSr DTACK DSr D LDTACK D LDTACK 00 00 01 01 11 11 10 10 00 00 01 01 11 11 10 10 Karnaugh map for LDS LDS = 1 LDS = 0 - - - 0 0 - 1 1 - - - - - - - - 1 1 1 - - - - - 0 0 - 0 0 0 - ?

  19. State encoding conflicts 0  1 LDS+ 0  0 LDTACK- LDS- LDS- LDS- LDTACK+ 1  0 10110 10110 1  1

  20. DSr+ DSr+ DSr+ Concurrency reduction LDS+ LDS- LDS- LDS- 10110 10110

  21. Concurrency reduction DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS-

  22. State encoding conflicts LDS+ LDTACK- LDS- LDTACK+ 10110 10110

  23. CSC+ CSC- Signal Insertion LDS+ LDTACK- LDS- LDTACK+ 101101 101100 D- DSr-

  24. Decomposition • Hazards • Global acknowledgement • Generating candidates • Hazard-free signal insertion • Event insertion • Signal insertion

  25. abcx 1000 b+ 0 1 0 1 0 0 0 1 a 0 0 1 1 0 0 1 1 z 1100 1 1 b x 1 1 1 0 1 1 1 0 0 0 0 0 0 1 c a- 0 0 1 1 0 1 0 1 0100 c+ 0110 Hazards 1000 1100 1100 0100 0110

  26. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z b a a y b d Global acknowledgement

  27. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z b a a y b d How about 2-input gates ?

  28. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? c z b a a y b d

  29. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? 0 c 0 z b a a y b d

  30. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? c z b a a y b d

  31. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- a b How about 2-input gates ? c z y d

  32. Strategy for correct logic decomposition • Each decomposition defines a new internal signal of the circuit • Method: Insert new internal signalssuch that • After resynthesis,some large gates are decomposed • The new specification is SI-implementable(hazard-free under unbounded gate delays)

  33. Decomposition -Boolean relations - Algebraic factorization Sr D C C D C Sr Sr D C Hazard-free ? (Signal insertion) C NO YES F until no more progress

  34. Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition (Boolean relations) Decomposition -Boolean relations -Algebraic factorization Sr F D C until no more progress Sr D C Hazard-free ? (Signal insertion) C NO YES

  35. h1 x1 x1 f F f H G xn xn hm Boolean decomposition f = F (x1,…,xn) f = G(H(x1,…,xn)) Our problem: Given F and G, find H

  36. h1 C f h2 state f next(f) (h1,h2) s1 0 0 (0,-) (-,0) s2 0 1 (1,1) s3 1 0 (0,0) s4 1 1 (-,1) (1,-) dc - - (-,-) This is aBoolean Relation

  37. y- a a+ c- c y d d- a- c+ a+ S y Rs y+ c- R a- d+ c+ F

  38. y- a a+ c- c y d d- a- c+ a a+ c y d Rs y+ c c- a- d d+ c+

  39. y- a a+ c- c y d d- a- c+ a+ y Rs y+ c- a- d+ c+ a

  40. y- a a+ c- c y d d- a- c+ a+ y Rs y+ c- D a- d+ c+ a d c

  41. Ad hoc solver for Boolean Relations • Existing solvers [Somenzi,Watanabe] aim at minimizing PLA size • Our approach: • Targeted to 2-output functions • Individual minimization of each function • Branch-and-bound to eliminate incompatible solutions (heuristic pruning) • Yields several solutions with similar cost

  42. Sr D C Sr D C Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) Hazard-free ? (Signal insertion) C NO YES Decomposition -Boolean relations -Algebraic factorization F until no more progress

  43. SR(x) b a x x x x a c b ER(x) Event insertion (Vanbekbergen’92)

  44. a a b b b a b a Event insertion (Continued) • Properties to preserve during insertion: • trace equivalence • speed-independence • output-persistency • commutativity • Signal insertion = a few events insertion

  45. a a a b b b x b b b a a a x a a b b b x a b b b a a b a Event insertion: examples a is not persistent a is persistent

  46. F+ F=0 F=1 F- Signal insertion for function F Insertion by input borders State Graph

  47. y- y- 1001 1011 z- w- 1000 0001 w+ y+ w- z- x+ z- w- w+ 1010 0000 0101 0011 w- y+ x+ z- y+ x+ x- 0010 0100 x- x+ y+ z+ 0110 0111 z+

  48. x y- y- y- y w 1001 1001 1001 1011 1011 1011 z z- z- z- w- w- w- y 1000 1000 1000 0001 0001 0001 w+ w+ w+ z y+ y+ y+ x w- w- w- z- z- z- x+ x+ x+ w 1010 1010 1010 0000 0000 0000 0101 0101 0101 0011 0011 0011 w w- w- w- y+ y+ y+ x+ x+ x+ z- z- z- C z y z 0010 0010 0010 0100 0100 0100 x- x- x- x+ x+ x+ y+ y+ y+ y z+ z+ z+ C 0110 0110 0110 0111 0111 0111 x z y yz=0 yz=1

  49. x y- y w 1001 1011 z z- w- y 1000 0001 w+ z y+ x w- z- x+ w 1010 0000 0101 0011 w w- y+ x+ z- C z y z 0010 0100 x- x+ y+ y z+ C 0110 0111 x z y yz=0 yz=1

  50. x y- w 1001 1011 y z- w- z 1000 0001 w+ y+ x w- z- x+ w 1010 0000 0101 0011 w w- y+ x+ z- C z y z 0010 0100 x- x+ y+ y z+ C 0110 0111 x z y yz=0 yz=1 z is delayed by the new signal !!!

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