1 / 25

Process-Aware 1-D Standard Cell Design

Process-Aware 1-D Standard Cell Design. Hongbo Zhang and Martin D. F. Wong Dept. of Electrical and Computer Engineering University of Illinois at Urbana-Champaign hzhang27@illinois.edu. Theme/Task: 1821.001 . Dense Line Printing and 1-D Cell Design.

tivona
Download Presentation

Process-Aware 1-D Standard Cell Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Process-Aware 1-D Standard Cell Design Hongbo Zhang and Martin D. F. Wong Dept. of Electrical and Computer Engineering University of Illinois at Urbana-Champaign hzhang27@illinois.edu Theme/Task: 1821.001

  2. Dense Line Printing and 1-D Cell Design • More regular geometric patterns are required in advanced cell design • Based on dense line printing technology, 1-D patterns can be printed by specialized dipole or annular light source • Good for cell composition/decomposition 2D patterns Hard to decompose Hard to print 1D patterns Easy to decompose Easy to print Techcon 2009,Session 5.5

  3. Dense line printing (gap free) • EPE: 1.224nm (-0.1um~0.1um defocus) Dense line printing with gaps Dense Line Printing • Dry, dipole, 0.93NA, 193nm, σ= 0.9, 115nm pitch, 32nm width T.A. El-Moselhy et. al, A capacitance solver for incremental variation-aware extraction, ICCAD 2008 Techcon 2009,Session 5.5

  4. Gap Size Matters • Increase of gap size will degrade printability • Increase EPE • Reduce Process windows • One direct way: insert dummies into large gaps Techcon 2009,Session 5.5

  5. Defocus = 0nm Defocus = 100nm Gap Pattern Matters • Certain gap patterns will destroy printability Techcon 2009,Session 5.5

  6. a b c d e f g I II III IV V VI Test Structures for Different Gap Distributions Techcon 2009,Session 5.5

  7. Small difference between a and b at 100nm defocus Simulation Results for Test Structure I and II • Process windows have slight difference between test I and test II • Gap has small impact on adjacent wire b a I II Techcon 2009,Session 5.5

  8. Not much difference Simulation Results for Test Structure II, III, IV and V • Process windows have not much difference • Gaps can be aligned together to reduce the impact on printability c b II III e d IV V Techcon 2009,Session 5.5

  9. g f e • Huge difference Simulation Results for Test Structure V and VI • Process windows have huge difference • A bad distribution will destroy the process window V VI Techcon 2009,Session 5.5

  10. Gap Classification • Regular gap • When a gap is adjacent to a real wire • Critical gap • When a gap is adjacent to a real wire’s line-end regular gap critical gap real wire real wire or dummy Techcon 2009,Session 5.5

  11. Rules for 1-D Cell Design • Insert dummies into empty space • Make gap size small and uniform • But more work can be done • Extend line-end to adjust gap distribution • Adjacent to a real wire • Align gaps together to reduce the impact • Reduce the number of regular gaps • Avoid certain gap patterns • Avoid critical gaps Techcon 2009,Session 5.5

  12. An Example • On-grid cell design • Properly extend wire and insert dummy wire segment to reduce # of regular and critical gaps A typical example of AOI21 Techcon 2009,Session 5.5

  13. Wire Extension Methodology • Wires can be represented by intervals • Only local region is concerned when judging a regular/critical gap • Wire end can be extended until a regular gap is removed or it cannot be extended any more. • Only the original wires rather than extension parts are concerned for gap hazard. • The remaining empty space will be filled with dummy in order to keep the uniform pitch Techcon 2009,Session 5.5

  14. A A A Algorithm I • A simplified algorithm without considering critical gaps • Sensitive region is limited to 2 continuous grids and 2 adjacent tracks • Regular gap is detected on case a and b • Extension sequence is not important • Always extend one side of line-ends first and then do the other side next a b c √ √ Techcon 2009,Session 5.5

  15. Real Wire Extension Dummy Algorithm I • Wire extension and dummy insertion Original Extend left end Dummy insertion Extend right end Techcon 2009,Session 5.5

  16. a b A A B B Algorithm II • A more complete version for considering critical gaps • Two forbidden patterns of critical gaps • In case of line-end A & B • Line-ends should be push far apart (a) or aligned together (b) • Only real wire’s line-end is concerned • Extension will help to prevent forbidden patterns, but dummy insertion will not Techcon 2009,Session 5.5

  17. Algorithm II: Initialization • Initialization is required to remove all critical gaps in the beginning • Case I: • Solution: • Do the left/right line-end extension to every wire first • One of A or B will be automatically extended • Case II: • Solution: • No more room can be applied for extension • Redesign is needed Techcon 2009,Session 5.5

  18. Algorithm II: Initialization • Case III: • Solution: • Before regular line-end extension is started, extend the line-end A • Critical gaps are removed initially Techcon 2009,Session 5.5

  19. Algorithm II • Always start extending the left line-end from the left most ones • Once a line-end is extended, the corresponding critical gap will be removed • Avoid misjudgement of the forbidden patterns • Extend the line-end until the gap is no longer adjacent to a real wire or it can not be extended any more • Critical gap should not be created during extension Techcon 2009,Session 5.5

  20. Optimality • Theorem: Algorithm II guarantees # of critical gaps is minimized. Moreover, among all solutions with minimum # of critical gaps, algorithm II produces minimum # of regular gaps. Techcon 2009,Session 5.5

  21. Experimental Results • Compare EPE between 1-D circuits with and without wire extension • 33.8% is saved for 32nm, 47.9% is saved for 45nm 45nm process: Pitch = 115nm, NA = 0.92 32nm process: Pitch = 75nm, NA = 1.40 Techcon 2009,Session 5.5

  22. Experimental Results • Algorithm I • Run time • Algorithm II Techcon 2009,Session 5.5

  23. Conclusion • Gap distribution is an important factor on 1-D cell design • Extension and dummy insertion is an effective way to rearrange gaps and benefit printing • Adjacent cells would interact with each other, but this extension and dummy insertion will help • Great improvement on printability has been shown Techcon 2009,Session 5.5

  24. Ongoing work • Study impact on circuit performance • Consider more constraints on wire extension: • Cross talk/noise • Limited extension • Explore wire permutation to obtain better cell structure Techcon 2009,Session 5.5

  25. TechTransfer • Liaison Interactions • Publications/presentations • H. Zhang, M. D. F. Wong, On Process-Aware 1-D Standard Cell Design, ASPDAC 2010 (to appear) • H. Zhang, M. D. F. Wong, K.-Y. Chao, L. Deng, and S.-H. Choi. Uniformity-aware standard cell design with accurate shape control. Proc. SPIE 7275, 72751G (2009) Techcon 2009,Session 5.5

More Related