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Ch.3 Overview of Standard Cell Design

Ch.3 Overview of Standard Cell Design. TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology. 4.1 Design Style. Design Method. Standard Design --------- Design by maker’s spec. Full Custom Design ------ Design of all masks by customer’s spec.

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Ch.3 Overview of Standard Cell Design

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  1. Ch.3 Overview of Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

  2. 4.1 Design Style

  3. Design Method • Standard Design ---------Design by maker’s spec. • Full Custom Design ------ Design of all masks by customer’s spec. • Manual Design • Cell-Based Design • Custom Cell/ Full Custom Design • Standard Cell Design • Semi Custom Design ----- Design of routing wire & logic functions by customer’s spec. • Gate Array • FPGA Design

  4. Standard Cell Design • Design Using Standard Cell, pre-design by professionals. • Cells includes Verilog, Circuit, Layout Information for NAND, NOR, D-FF • Logic Design and Layout Design done by CAD. • Logic Design --- by use of Cells with specified delays • Layout Design – by use of Cells • Generated Data is mainly interconnection wires.

  5. List of Standard Cells • Decoder 2 to 4 • Half Adder 1bit • Full Adder 1bit • Pos Edge DFF • Neg Edge DFF • Scan Pos Edge DFF • Scan Neg Edge DFF • RS NAND Latch • High-Active • Clock Gating Latch • Non-inverting Delay line • Pass Gate • Bidirectional Switch • Hold 0/1 Isolation Cell • Inverter • Inverting Buffer • Non-inverting Buffer • Tri-state Non-inverting Buffer • AND 2, 3, 4 inputs • NAND 2,3,4 inputs • OR 2, 3, 4 inputs • NOR 2,3,4 inputs • XNOR 2,3 inputs • AND-OR • AND-OR-Inverter • OR-AND • OR-AND-Inverter • Multiplexer 2 to 1 • Multiplexer 4 to 1

  6. Standard Cell Design Logic gates, latches, flip-flops, or larger logic Routing channels

  7. Layout

  8. Place & Rout

  9. Standard Cell Library • Circuit description at RTL level • Layout description in GDSII format • TLF Format Data • Logical information • Transistor and interconnect parastics • Spice netlist • Power information • Process, temperature and supply voltage

  10. 4.2Cell

  11. Library Design Flow I Mask Data GDSII Layout Design Cell Information Technology information Abstract Generator Library Data LEF Extraction Circuit Data Netlist I/O delay paths Timing check values Interconnect delays Analog Environment Circuit Data TLF

  12. Library Design FlowII Physical Layout (gdsII, Virtuoso Layout Editor) Should follow specific design standards eg. constant height, offsets etc. Logical View (verilog description or TLF) Verilog is required for dynamic simulation. Place and route tools usually can use TLF.Verilog description should preferably support back annotation of timing information. Abstract View (Cadence Abstract Generator, LEF) LEF: Contains information about each cell as well as technology information Timing, power and parasitics (TLF) Transistor and interconnect parasitics are extracted using Cadence or other extractiontools (SPACE).Spice or Spectre netlist is generated and detailed timing simulations are performed.Power information can also be generated during these simulations.Data is formatted into a TLF file including process, temperature and supply voltagevariations.

  13. Library Exchange Format (LEF) • An ASCII data format, used to describe a standard cell library includes the design rules for routing and the Abstract of the cells, no information about the • internal netlist of the cells • Technology: layer, design rules, via definitions, metal capacitance • type: Layer type can be routing, cut (contact), masterslice (poly, active), overlap. • width/pitch/spacing rules • direction • resistance and capacitance per unit square • antenna Factor • 2. Site: Site extension • ３．Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.

  14. Timing Library Format (TLF) • TLF is an ASCII representation of the timing and power parameters associated with any cell in a particular semiconductor technology. The timing and power parameters are obtained by simulating the cells under a variety of • conditions and the data is represented in the TLF format、 • The TLF file contains timing models and data to calculate • I/O delay paths • Timing check values • Interconnect delays

  15. Standard Cell I

  16. Standard Cell II

  17. Layout

  18. Cell Design Flow VHDL Model VHDL -> Verilog Conversion Synopsys Design Compiler Verilog Model Standard Cell Placement Cadence Design Planner DEF File Standard Cell Routing Cadence Silicon Ensemble DEF File Export to Other Formats, SPICE Verification Cadence ICFB Verilog Model Verilog Verification Modelsim

  19. Layout Condition

  20. DC Characteristic Low slope -1 VOHMIN VOHMIN High slope -1 VOLMAX VOLMAX VILMAX VIHMIN WLT

  21. Propagation Delay with loads

  22. 4.2LSI Design Procedure

  23. Logic Design RTL RTL Simulation Logic Synthesis Synthesis Netlist Functional Verification Scan Path Design Functional Verification Scan Netlist Timing Analysis

  24. Layout Design Netlist Layout Design Functional Verification Layout Netlist Gate Level Simulatior ATPG Mask Data DRC/LVS Test Pattern

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