The GANDALF Multi-Channel Time-to-Digital Converter (TDC)

1. The GANDALF Multi-ChannelTime-to-Digital Converter (TDC) Sebastian Schopferer University of Freiburg TIPP 2011, Chicago June 13, 2011 • GANDALF module • TDC concepts • TDC implementation in the FPGA • measurements

2. The GANDALF module Generic Advanced Numerical Device for Analog and Logic Functions Virtex-5 SX95T FPGA for Data Processing: 60k CLB flip-flops, 8 Mbit Block RAM, 640 DSP Slices, 500 MHz mezzanine card slot 1 VME64x Interface VITA 41.0 VXS Interface Virtex-5 LX30T FPGA for Memory Control& Data Output: 20k CLB flip-flops, 1.2 Mbit Block RAM, 500 MHz USB 2.0 TCS mezzanine card slot 2 S-Link Interface to DAQ Memory: 144 MbitQDRII+, 4 Gbit DDR2 Sebastian Schopferer

3. The GANDALF module • GANDALF transient recorder • 16 analog inputs for A/D conversion (500 MS/s @ 12 bit) • optional time-interleaved mode: 8 channels with 1000 MS/s • real-time pulse shape analysis with online feature extraction (time resolution up to 10 ps) • GANDALF with digital inputs / outputs • 128 differential inputs or outputs • module functionality is free programmable in the FPGA • e.g. time-to-digital converter, scaler, mean-timer, coincidence matrix, pattern generator • combinations of these functionalities are possible for cost efficient design Sebastian Schopferer

4. Digital Mezzanine Card (DMC) • buffer card to convert signal levels and protect FPGA from short circuits and ESD • 2 x 32-channel VHDCI connectors • 64 differential inputs (e.g. LVDS, LVPECL) or 64 differential outputs (LVDS) • 1x NIM input, 2x NIM outputs • jitter < 20 ps (including FPGA inputs) Sebastian Schopferer

5. GANDALF TDC design objectives • 128 TDC channels per board • time resolution better than 100 psrms • leading and/or trailing edge sensitivity • multi-hit capability • 10 ns double hit resolution • 18bit dynamic range • 20 µs look-ahead / look-back hit buffer • programmable trigger window • dead-time free data readout more about the GANDALF module: http://hadron.physik.uni-freiburg.de/gandalf/ Sebastian Schopferer

6. TDC concepts Trivialconcept of TDC sampling of data signal  TDC bin width = 1/fmax ≈ 2 ns fmax: 500 MHz (Virtex-5) reduce TDC bin width by: Delayed Data Sampling Shifted Clock Sampling • equidistant delay of data signal ∆tdelay = 1/(n*fclk) • same clock signal at all flip-flops • equidistant phase shift of clock signal φdelay = 2π/n • same data signal at all flip-flops Sebastian Schopferer

7. Shifted Clock Sampling data signal Hit 8 phase shifted TDC clocks 8 TDC flip-flops output register check for ‘bit pattern’ ≠ “00000000” or “11111111” bit pattern “11000000”  hit detected! time(TDC bin) = clk_counter * 8 + ‘bitswap’ position Sebastian Schopferer

8. Partitions • eight different clock domains • register outputs are not stable simultaneously • readout not possible at a single point in time • “partitions” are introduced to merge the clock domains in a two-stage process ‘overlap’ avoids loss of hits! Setup & hold readout 0 1 2 3 4 5 6 7 0 0 7 1 2 6 partition 0 partition 1 3 5 4 Setup & hold readout Sebastian Schopferer

9. Implementation Challenge • accuracy of TDC bin width influenced by  clock „phase error“  „routing delay“ of data signal routing resources 8 TDC-flip-flops routing of data signal to TDC flip-flops • placement is user-controlled by scripts • auto-router finds appropriate connections Sebastian Schopferer

10. Implementation Phase-shifted clocks produced by two PLLs clock 0º clock 90º clock 180º clock 270º PLL 1 clock 45º clock 135º clock 225º clock 315º PLL 2 Sebastian Schopferer

11. Trigger Matching • time stamp measurements • select only hits within a time window around a trigger signal • trigger signal can be related to data in the past (“look-back”) or in the future (“look-ahead”)  hit data storage inside FPGA needed • max. latency: 20 µs • HIT FIFO depth: 1k Sebastian Schopferer

12. TDC overview clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 TDC register(8 flip-flops) Data partition0 partition1 Hit Buffer RAM ClockCounter Trigger Matching Trigger TDC channel Output FIFO merge 128 channels DAQ Sebastian Schopferer

13. FPGA resource usage average resource usage per TDC channel 1 TDC channel Sebastian Schopferer

14. Measurement Setup TDC Input (LVDS) Pattern Output (LVDS) • clock frequency 388.8 MHz • 8 phase-shifted clocks •  TDC bin width: 320 ps TCS in Pattern Generator (output) TDC GANDALF (input) Sebastian Schopferer

15. Measurements Differential Nonlinearity PLL1 not optimized: PLL2 optimized: Sebastian Schopferer

16. Extension to 16 TDC bins • clock frequency 388.8 MHz • 2 flip-flops per slice • 8 phase-shifted clocks + 8 inverted clocks •  TDC bin width: 160 ps 0 7 1 6 2 3 5 falling-edge-triggered rising-edge-triggered partition 1 partition 0 4 4 5 3 6 2 1 7 0 Sebastian Schopferer

17. 128 channels with 16 TDC bins Differential Nonlinearity Sebastian Schopferer

18. TDC time resolution • RMS of the time stamp difference between ‘channel n’ and the mean of all other channels: TDC time resolution < 0.5 * LSB = 80 ps for comparison: resolution of ideal TDC =1 / sqrt(12) * LSB = 46 ps Sebastian Schopferer

19. Conclusion design objectives achieved: • 128 TDC channels in the GANDALF Virtex-5 FPGA • TDC bin width: 160 ps • DNL < 0.2 LSB = 32 ps • time resolution < 80 psrms under progress: • integrate 128 scaler channels into the same design • inter-board communication via VXS for fast trigger decisions • design migration to Artix-7 or Kintex-7 (front-end solution) more about the GANDALF module: http://hadron.physik.uni-freiburg.de/gandalf/ Sebastian Schopferer