Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation Jins Davis Alexander

1. Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation Jins Davis Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 SSST'09

2. Objective • Determine power dissipation in a digital CMOS circuit. SSST'09

3. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Ptotal = Pdyn + Pstat = Ptran +Psc + Pstat SSST'09

4. Power Per Transition isc VDD Dynamic Power = CLVDD2/2+ Psc R Vo Vi CL R Ground SSST'09

5. Number of Transitions SSST'09

6. Problem Statement • Problem - Estimate dynamic power consumed in a CMOS circuit for: • A set of input vectors • Delays subjected to process variation • Challenge - Existing method, Monte Carlo simulation, is expensive. • Find a lower cost solution. SSST'09

7. Bounded (Min-Max) Delay Model IV FV IV FV EA LS EA LS • EA is the earliest arrival time • LS is the latest stabilization time • IV is the initial signal value • FV is the final signal value EAsv=-∞ LSsv=∞ Driving value [d, D] EAdv LSdv EAdv=-∞ LSdv=∞ Sensitizing value EAsv LSsv SSST'09

8. Example d D d D SSST'09

9. Finding Number of Transitions 3 14 7 10 12 14 2, 2 5 8 10 12 [mintran,maxtran] [0,2] 3 14 6 17 1, 3 EA LS EA LS [0,4] 5 17 EA LS where mintran is the minimum number of transitions and maxtran the maximum number of transitions. SSST'09

10. Estimating maxtran • Nd: First upper bound is the largest number of transitions that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output values. • N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further modify it as N = N – k where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs. • The maximum number of transitions is lower of the two upper bounds: maxtran = min (Nd, N) SSST'09

11. First Upper Bound, Nd Nd = 1 + (LS – EA)/d └┘ d, D d EA LS SSST'09

12. Examples of maxtran Nd = 1 + (18 – 3)/0 = ∞ N = 4 + 4 = 8 maxtran=min (Nd, N) = 8 Nd = 1 + (23 – 6)/3 = 6 N = 4 + 4 = 8 maxtran=min (Nd, N) = 6 SSST'09

13. Example: maxtran With Non-Zero k [n1 = 6] [n1 + n2 – k = 8 ] , where k = 2 EAsv = - ∞ LSdv = ∞ EA LS EAdv LSsv [n2 = 4] LSdv = ∞ EAsv = - ∞ EAdv LSsv [ 6 ] [ 6 + 4 – 2 = 8 ] [ 4 ] SSST'09

14. Simulation Methodology • d, D = nominal delay ± Δ% • Three linear-time passes for each input vector: • First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals. • Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays. • Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information. SSST'09

15. Zero-Delay Vs. Event-Driven Simulation SSST'09

16. Maximum Power • Monte Carlo Simulation vs. Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). R2 is coefficient of determination, equals 1.0 for ideal fit. SSST'09

17. Minimum Power R2 is coefficient of determination, equals 1.0 for ideal fit. SSST'09

18. Average Power R2 is coefficient of determination, equals 1.0 for ideal fit. SSST'09

19. C880: Monte Carlo vs. Bounded Delay Analysis 1000 Random Vectors, 1000 Sample Circuits SSST'09

20. Power Estimation Results • Circuits implemented using TSMC025 2.5V CMOS library , with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. SSST'09

21. Conclusion • Bounded delay model allows power estimation method with consideration of uncertainties in delays. • Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. SSST'09