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Tracker Off-detector Electronics

On-detector electronics production approaching completion procuring spares Off-detector electronics FED & FEC development complete substantial software development Power supplies prototyping of cavern version successful tender action complete ESRs completed

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Tracker Off-detector Electronics

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  1. On-detector electronics production approaching completion procuring spares Off-detector electronics FED & FEC development complete substantial software development Power supplies prototyping of cavern version successful tender action complete ESRs completed final one: Off-detector electronics November 2003 Grounding and shielding Fine tuning of systems already demonstrated in lab and beam tests Tracker Off-detector Electronics Geoff Hall

  2. FEDv1 -first prototype • 9U VME64x • PCB 14 layers (incl 6 power & ground) • ~ 6 K components (smallest 0402) ; ~ 25 K tracks • BGAs largest 676 pins @ 1 mm pitch • 96 ADC channels : • AD9218 Dual package 10 bit @ 40 MHz • Half Analogue circuitry on Secondary Side • JTAG Boundary Scan • 6 FEDv1 boards delivered to CERN for Large Scale Assembly centres (4 used in 25 nsec test beam June 2004) • 5 FEDv1 boards kept in UK for Design Tests Geoff Hall

  3. FEDv1 Manufacture History • Sep 2003 • 5 FEDv1 boards under test. (PCB and Assembly by separate small companies) All boards working well. Only manufacturing minor faults. • Oct 2003 • Further 6 FEDv1 made. (same manufacturers) Major problems on all boards. Shorts under many BGAs. Rework of BGAs attempted. After initial success on 2 boards failed on next 4. Problem believed due to uncured solder resist ink leeching from vias of bare PCBs. Precise diagnosis difficult, plus change of metal finish (Ni/Gold -> Immersion Tin). • Nov 2003 - Jan 2004 Identified candidate medium size companies suitable for 500 production boards. Providing combined PCB and Assembly with guarantees. Offer advanced Quality Controls, Auto Optical Inspection, X-ray (in house), BScan. • Mar 2004 • Manufactured 6 FEDv1 with one identified company. Very professional production. No BGA problems. All boards working well. Geoff Hall

  4. FEDv1 Design Testing • Objectives • Validate final design done • large scale assembly acceptance tests under way • Hardware few issues studied and resolved during testing Verified @ 100 kHz L1 S-LINK readout @ 80 MHz. TTC and TCS Interfaces verified Analogue performance excellent. Optical inputs using FED Opto-Tester board. To optimise OptoRx (1% settling in 15ns) some FE component values need final tuning. Power/temp requirements finalised. Standard LHC crates satisfactory. • Firmware complete and working for assembly test use Used in 25 nsec Test Beams June 2004. Few minor issues (as expected!) under investigation. • Software fully integrated in CMS Tracker DAQ framework. Test bench Framework for essential Assembly Plant Testing nearly ready Geoff Hall

  5. FEDv2 pre-Production Board • Aim to be final production version - minimal changes from v1 • Power Block : General improvements. • QDR Memory : Replacement part (pin compatible) identified. • FE FPGA : Use larger 2M gate (pin compatible) part. • ADC : AD9218 Device bug. Reduce gain by half. Simple mod. • FPGA Configuration : VME Boot device reprogram via JTAG cable. • S-LINK & TCS Signals : New 6U VME Transition Card. • FE Analogue : Tune few components for optimal matching to Optical Link • Status First 2 boards received in August. Tests proceeding well. Boundary Scan passed. VME crate tests in progress • Plan to make a further ~20 before end of 2004 for Full Crate tests. Geoff Hall

  6. Testing at Assembly Plant Testing by Assembly plant operatives 0. Quality Controls during Assembly process Boundary Scan Testing for Digital AOI, X-ray 1. Custom Tests at Assembly Plant BScan, VME crate 2. Tests at RAL & IC OptoRx, Full crate 3. Tests at CERN Prevessin Readout Integration VME Crate Testing for Analogue 4. Installation at CMS USC55 Test Flow from Assembly Plant to USC55 500 boards to test over 10 months. Essential to catch any manufacturing faults early. Geoff Hall

  7. FED Schedule (v 1.6 March 2004) Production Plans Q1/2004 : Complete tests of FEDv1 design. Done. Finalise design changes for FEDv2. Done. Sign off against FED User Requirements Document. Done. Q2/2004 : Implement changes for FEDv2 and review. Done. Q3/2004 : Manufacture couple of FEDv2s. Done. Q4/2004 : Test FEDv2. In progress. Manufacture further 20 FEDv2s. All parts in hand except QDR memories on order. Q2/2005 -> Q2/2006 : Manufacture 500 FEDs @ ~ 50 / month. Fully test batches in UK. Ship to CERN in batches of 50. Re-test at CERN/Prevessin prior to CMS installation. EU Tender Procedure for PCB/Assembly Q1/2004 : Place OJEC advert, invite Expressions of Interest.Done. Q3/2004 : Dispatch calls for Quotes. Identify 2-3 companies. In progress. Q4/2004 : Select company. Detailed negotiations re Testing, delivery schedules…etc Q1/2005 : Award contract. Expect to tune this schedule in response to availability of B904 and USC55 Geoff Hall

  8. mFEC mFEC mFEC mFEC mFEC mFEC mFEC mFEC VME FEC See also Kostas Kloukinas ECAL AR for all details • Support for 1~8 control rings per board. • VME 9U board. • VME64x compatible. • Control information passes through the VME bus. • Fast Timing Signals passes through the TTC link. VMEinterfaceFPGA Local Bus VMEbus JTAG Fast Timing signals TriggerFPGA QPLL TTCrx Now use for TK + ECAL, pixels, Preshower TTC link ECAL TTC/TTS bus Geoff Hall

  9. VME FEC 1st Prototype VME Interface FPGA 6 Layer board mFECs Final version and already in use VME backplane TTC/TTS bus TTC input Trigger FPGA Geoff Hall

  10. FEC Production • Tracker: 352 control rings: 44 VME FEC boards + spares • total with ECAL, etc 112 VME boards + 950 mFECs • First VME PCB prototype: work, but manufacturing issue • excessive bending after thermal cycle (solder components) • VME FEC Pre-Production PCBs at CERN this week. • adjusted stacking of the FR4 layers • mFEC Pre-Production Run (50 off) • Available late September. • Final Production (PCB fabrication + assembly + testing) • mFECs Jan. 2005 - Jun. 2005 • FEC boards Jan. 2005 - Jun. 2005 Geoff Hall

  11. Two prototypes produced Cavern and counting room variants Performance looks excellent B-field tests done Radiation tests done Lab tests show good performance noise isolation hardware protection and current limiting overvoltage protection efficiency 70-85% (load dependent) used in beam tests with long cables giving excellent results Power supplies Geoff Hall

  12. Variants very similar - one allows cavern operation Sufficiently B-field and radiation tolerant Recent improvements in transformers optimise size Modules Geoff Hall

  13. Tender action complete Technical performance of two variants essentially identical Cavern Supply had required magnetic field and radiation tolerance Cost saved by PS in the Cavern was between 1.5 - 3.0 MCHF.. Cavern solution adopted June 2004 INFN adjudication committee accept CAEN offer Production - if order placed before October 2004 Begin Q4 2004 Ramp to ~65 /month Complete deliveries in Q1 2006 Tender & Schedule Geoff Hall

  14. Delivery Schedule Provided that orders are placed by 30 September 2004 Red = SST + pixels 2004 2005 2006 Geoff Hall

  15. Separate detector support activities from commissioning Stable DAQ and hardware needed for large scale assembly Prevessin 904 for pre-commissioning phase USC55/UXC for final phase NB TK DAQ essentially ready and working (XDAQ) Adapt plans to availability of space and plant Eg FEDs Quality control in company during assembly Tests at assembly plant (JTAG, Self Test) Crate and software provided by IC-RAL, tests all functionality except ORx’s Final acceptance of boards at Imperial and RAL optical tests, and soak test Test at CERN 904 with FEC, TTC, trigger etc should verify previous results prior to move to cavern Installation in system at CERN Commissioning Geoff Hall

  16. No showstoppers in sight Well advanced with hardware, pre-production, evaluation and integration, including software Production plans almost complete Main issues Quality of production (and associated cost & effort) Adapting commissioning plans to requirements Conclusions Geoff Hall

  17. Spare slides Geoff Hall

  18. 12 12 12 12 12 12 12 12 FED Overview Input ~ 3 GBytes/sec after Zero Suppression : Output: ~ 200 MBytes/sec Modularity 9U VME64x Form Factor Modularity matches Opto Links 25,000 Si strips / FED 440 FEDs in Total. 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-Endmodule / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration 96 Tracker Opto Fibres CERN Opto- Rx 9U VME64x Analogue/Digital JTAG FPGA Configuration Compact Flash FE-FPGA Cluster Finder VME Interface VME-FPGA BE-FPGA Event Builder TCS TTC TTCrx DAQ Interface Buffers Power DC-DC Temp Monitor Front-End Modules x 8 Double-sided board Xilinx Virtex-II FPGA TCS : Trigger Control System

  19. Firmware and FPGAs Delay x 24 FE x 8 Baseline of 4 FPGA Final Designs working... VME x 1 BE x 1 34 Xilinx Virtex II FPGAs up to 2M equiv gates each Delay FPGA: ADC Coarse and Fine Clock Skewing. FE FPGA: Scope and Frame Finding modes. BE FPGA: Event building, buffering and formatting. VME FPGA: Controls and Slow Readout path. Geoff Hall

  20. S-LINK VME Transition Card • Simple 6U board: • Provides interface between FED and Slink Transmitter • Provides access to FED Throttle signals VME Backplane Slink Transition Card FED Slink Data & Control Signals DAQ Slink Transmitter 6U FED Throttle Signals Ethernet Connector 3 Transition Cards in manufacture by end July. Now back for test in September. (compatible with both FEDv1 and FEDv2) Geoff Hall

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