Stacked-Die Chip Scale Packages

1. Stacked-Die Chip Scale Packages Adeel Baig

2. Objectives • Define Stacked-Die Chip Scale Packages (S-CSP) • Explain the need for S-CSP • Define the challenges faced • Present strategies for improving the electrical performance and yield of wire bound S-CSP Microsystems Packaging

3. S-CSP • S-CSP refers to a type of multi-die package in which the die are stacked vertically and interconnected electrically via wire bonding in most cases. Microsystems Packaging

4. S-CSP Microsystems Packaging

5. Why Wirebonding? • Advantages • Greater flexibility • More cost effective Microsystems Packaging

6. Why S-CSP? • For many hand held devices, there is a need for greater functionality crammed into a smaller package. • These features require • Greater memory capacity • Smaller footprint • Thinner profile • Lower package cost Microsystems Packaging

7. Functions Added to Cell Phones Microsystems Packaging

8. Sensors in Cell Phones • MECHANICAL (Accelerometer) • Joystick games • Shock detectors • CHEMICAL • Pollution • Alcohol • OPTICAL • Imaging • Optical mouse • CAPACITIVE • Fingerprint detection Microsystems Packaging

9. Worldwide Cell Phone Sales(Millions) Microsystems Packaging

10. Challenges Faced • Increasing wire bond density • Additional space and height requirements for wire looping • Yield Issues • Wire shorting is the main cause of low yield in high-density packages • If one die fails, all of the other stacked and assembled dies are lost as well Microsystems Packaging

11. Key Factors • Wire Sweep • Bonded wires are misaligned in the horizontal plane. • Problems Created • The mutual inductance of adjacent wires can be altered and simultaneous switching noise can be created • An electrical short can occur when the wires touch. Microsystems Packaging

12. Key Factors • Wire Spacing • Distance between adjacent wires • Problems Created • If there is not adequate space between the wires, the risk of an electrical short is greatly increased. • If the wires are more likely to touch and short, a lower yield will result. Microsystems Packaging

13. Optimizing Design • Minimize Wire Length • With increased wire length, there is a greater possibility that wire sweep problems will develop • Greater wire length has an adverse effect upon electrical performance • The impedance will be increased • Inductive coupling will be more likely to occur • The package operating speed will be reduced Microsystems Packaging

14. Optimizing Design • By shifting the die location or moving the die with respect to another die, it is possible to reduce wire length while achieving greater die to die bonding • Option B results in lower wire length Microsystems Packaging

15. Optimizing Design • Die Setup • There are two main factors in the design process • Location of the die • The manner in which they are stacked. Microsystems Packaging

16. Optimizing Design • Optimizing performance by shifting die position. • Figure (b) eliminates a bond wire to pad short Microsystems Packaging

17. Optimizing Design • The die that has more stringent performance requirements should be placed on the bottom of the stack Microsystems Packaging

18. Wire Encapsulation • In order to maximize yield, it has been necessary to inspect wires for shorts and eliminate them. • Wire spacing is not an issue with this encapsulation technology. • Experiments show that using this method can reduce wire sweep and separate electrically shorted wires. Microsystems Packaging

19. Wire Encapsulation • A silica filled liquid polymer is dispensed onto the wires following the wire bonding process. • This material has many qualities that allow it to remain functional and reliable during the manufacturing process. • Adheres well • Has low moisture absorption • Minimized CTE mismatch that help to enhance reliability Microsystems Packaging

20. Wire Encapsulation Microsystems Packaging

21. Wire Encapsulation • Ring Lock method is superior • The amount of encapsulant material utilized can be greatly reduced by 80-95% • Less time is needed in the dispensing procedure Microsystems Packaging

22. Wire Encapsulation • Encapsulant can help fix wire shorts Microsystems Packaging

23. Wire Encapsulation • Results show that wire encapsulation increases yield Microsystems Packaging

24. Conclusion • Although flip chip technology seems superior, wire bonding is still widely used in the packaging and manufacturing industry. • Challenges faced in wire bonding S-CSP are becoming more complicated • By utilizing the two approaches (Design and Wire Encapsulation) jointly, it is possible to overcome these obstacles. Microsystems Packaging