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A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation

A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation. Viet L. Do and Kenneth Y. Yun. IEEE Transactions on Circuits and Systems for Video Technology, Vol.8, No.4, Aug 1998. Outline. Introduction Full-Search Block-Matching Process Conservative Approximation

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A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation

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  1. A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation Viet L. Do and Kenneth Y. Yun IEEE Transactions on Circuits and Systems for Video Technology, Vol.8, No.4, Aug 1998

  2. Outline • Introduction • Full-Search Block-Matching Process • Conservative Approximation • Low-Power VLSI Architecture • Simulation Results • Conclusion

  3. Introduction • Motion compensation technique reduce the coding bit-rate by eliminating temporal redundancy in video sequences • The full-search algorithm exhaustively checks all candidate blocks to find the best match within a particular window • Proposed method computes a conservative estimate of the exact distortion value for each candidate macroblock before computing the exact distortion

  4. Full-Search Block-Matching Process

  5. Conservative estimate of D(u, v) Partial estimate for the ith row of candidate macroblock (u, v) Conservative Approximation (1)

  6. Conservative Approximation (2)

  7. Low-Power VLSI Architecture

  8. Processing Element Array (1)

  9. Processing Element Array (2)

  10. Processing Element Array (3) Size of search area is (N+2w)2, but only (2w+1)2 candidate blocks are valid Need (N+2w-1)(N-1)+N cycles for initialization, and N-1 cycles for shift to next row

  11. Block-Matching Unit

  12. Distortion Approximation Unit

  13. Simulation Results (1) • Define a new measure of energy consumption: one unit of ADE(absolute difference equivalent) is the amount of energy consumed in computing one AD • One AD calculation is roughly equivalent to two additions • Calculating D(u, v) consumes 1.5N2 ADE • Computing PDi^(u+1, v) consumes ADE on average • Thus computing D^(u+1, v) consumes ADE • Therefore, the energy consumption for computing D^(u+1,v) is linear in N whereas the energy consumption for computing D(u,v) is quadratic in N

  14. Simulation Results (2) • Correlation: the pixels in the same relative positions of two consecutive candidate blocks have the same luminance values • Taking correlation into account, it reduces to 0.85*256+128 = 346 ADE • Low-power architecture implementation requires 45+0.426*346 = 192 ADE • Only 192/346 = 55% of that of conventional systolic architecture

  15. Simulation Results (3)

  16. Conclusion • The conservative approximation method that reduces power consumption in full-search block-matching motion estimation • Simulation results show that the proposed low-power VLSI architecture consumes half as much power as the conventional systolic array based architecture

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