A Novel Flash Analog-to-Digital Converter

1. A Novel Flash Analog-to-Digital Converter Adviser: Dr.Hsun-hsiang Chen Postgraduate : Chieh-En Lo

2. Reference • Chia-Nan Yeh; Yen-Tai Lai;Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on18-21 May 2008

3. Outline • Introdution • New ADC Architecture • New high bubble error tolerance encoder • Simulation Results

4. Introdution N • N-bit flash ADC replace the (2 -1)-to-N encoder with two (2 -1)-to-(N/2) encoder • A new encoding algorithm is proposed to enhance the bubble error tolerance of an ADC N/2

5. New ADC Architecture K • Tranditional K-bit TC-to-BC encoder has (2 -1) fan-in and K fan-out • We halve the encoding into two parts which are MSB and LSB • Each encoder processes 2 -1 input and k/2 output k/2

6. Example: 25(10) → 011∣001(2) (6 BIT) MSB LSB quotient remainder

9. New high bubble error tolerance encoder

10. = x + x + 1 +x = 1 = x + x + 0 +x =0 = x + 1 + 0 +x =1

11. for MSB reliability,we replace the original 2-input NAND with 3-input NAND

12. Simulation Results • standard CMOS 0.18μm 1P6M technology • supply voltage 1.8V • input range 1V

15. THE END