VHDL-AMS

1. VHDL-AMS VHDL-AnalogandMixedSignalExtensions

2. Overview • IEEE Std. 1076.1-1999: • Extension to VHDL to support the description and simulation of analog and mixed-signal circuits and systems • VHDL-AMS = IEEE Std. 1076.1-1999 + IEEE Std. 1076-1993 • VHDL-AMS is a strict superset of IEEE Std. 1076-1993 • Any model valid in VHDL 1076 is valid in VHDL-AMS and yields the same simulation results

3. Why Needed? • Many of today’s designs include at least some continuous characteristics: • System design • Mixed-signal electrical designs (Cell phones, …) • Mixed electrical/non-electrical designs (Music players, Digital Cameras, Samand) • Modeling design environment (Temperature, humidity, …) • Analog design • Analog behavioral modeling and simulation • Digital design: As frequency increases, and technology advances (DSM effects), digital circuits become more analog • Clock distribution (PLL’s, pulse shapers, oscillators) • Pad design (buffers, protection circuits) • Interconnect (become more like transmission lines) • Logic cells (become more like RF and microwave circuits) • Designers want a uniform description language

4. When Digital Becomes Analog? Frequency (GHz)

5. Issues in Mixed-Signal Circuit Design • As feature size decreases, RF circuit issues become dominant in both digital and analog circuits • Noise • Coupling noise • Component noise • Power supply and ground noise • Circuit parameters • Impedance mismatches • Gain •  Major need for analysis methods and tools

6. Current Status of Mixed-Signal Design • Fabrication technology: • Current technology supports mixed-signal circuits on a chip • And even mixed electro-mechanical systems on a chip (MEMS) • Design tools: • Analog and Mixed-Signal (AMS) modeling and simulation • AMS synthesis (still in research stage)

7. Advantages of Verification • Advantages of Modeling and Simulation: • Early error detection • Fine tuning the design based on verification output • Reliable time metrics can be obtained

8. Simulation in an M-S Environment • Challenges: • Multiple domains, multiple abstraction levels • Simulation cycle handles notion of time in discrete and continuous values • Separate simulation engines, working with the same set of signals

9. Highlights of VHDL-AMS • Inclusion of continuous valued “quantities” • Allows design entry at the behavioral or structural levels • Analog solution based on numerical integration • Continuous models based on “differential algebraic equations” (DAE)

10. Nature • Definition: • Nature represents a physical discipline/energy domain • Samples: • Electrical • thermal, • fluidic, • magnetic, • ….

11. Terminal • Terminal: • Represents a node in an electrical circuit

12. Quantity • Represents an unknown in the set of DAEs • May be the value (e.g. voltage level) across or through two terminals. • Continuous-time waveform. • For any quantity Q, the attribute name Q’Dot denotes the derivative of Q w.r.t. time. • Q’Dot is itself a quantity • Q’Integ: integral of Q w.r.t. time.

13. Simultaneous Statement • Simultaneous Statement: • Expresses relationship between quantities. • Analog solver is responsible for computing the values of the quantities such that the relationships hold (subject to tolerances) • May appear anywhere a concurrent statement may appear. • Statement is symmetrical w.r.t. its LHS and RHS. architecture H2 of Vibration is ... begin x1’dot’dot == -f*(x1 - x2) / m1; x2’dot’dot == -f*(x2 - x1) / m2; xs == (m1*x1 + m2*x2)/(m1 + m2); energy == 0.5*(m1*x1’dot**2 + m2*x2’dot**2 + f*(x1-x2)**2); end architecture H2;

14. Simultaneous Statement • Other Forms of Simultaneous Statements: • Simultaneous IF statement • Simultaneous CASE statement • Simultaneous procedural statement – functions ENTITY sfgAmp IS GENERIC ( gain: REAL := REAL’HIGH); PORT (QUANTITY input: IN REAL; QUANTITY output: OUT REAL); END ENTITY sfgAmp; ARCHITECTURE ideal OF sfgAmp IS BEGIN IF gain /= REAL’HIGH USE output == gain * input; ELSE input == 0.0; END USE; END ARCHITECTURE ideal;

15. Branch Quantities • Declared between two terminals • Plus terminal and minus terminal • Minus terminal defaults to reference terminal of nature • vd is an across quantity: • it represents the voltage between terminals anode and cathode • vd= vanode - vcathode • id and ic are through quantities: • they represent the currents in the two parallel branches • Both currents flow from terminal anode to terminal cathode architecture Level0 of Diode is quantity vd across id, ic through anode to cathode; ... begin ... end architecture Level0;

16. Example: Diode library IEEE, Disciplines; use Disciplines.electrical_system.all; use IEEE.math_real.all; entity Diode is generic (iss: REAL := 1.0e-14; n, af: REAL := 1.0; tt, cj0, vj, rs, kf: REAL := 0.0); port (terminal anode, cathode: electrical); end entity Diode; architecture Level0 of Diode is quantity vd across id, ic through anode to cathode; quantity qc: charge; constant vt: REAL := 0.0258; -- thermal voltage begin id == iss * (exp((vd-rs*id)/(n*vt)) - 1.0); qc == tt*id - 2.0*cj0 * sqrt(vj**2 - vj*vd); ic == qc’dot; end architecture Level0;

17. Quantities in Various Natures • Electrical • voltage: across • current: through • Translational • position: across • force: through • Thermal • temperature: across • power (or heat-flow): through • Fluidic • pressure: across • flow-rate: through

18. References • Reference Site: • http://www.vhdl-ams.org/ • Reference Book: • The System Designer's Guide to VHDL-AMS (The Morgan Kaufmann Series in Systems on Silicon) by Peter J. Ashenden, Gregory D. Peterson, Darrell A. Teegarden • Tools: • Mentor Graphics SystemVision: • a downloadable version for educational purposes: • www.mentor.com/SystemVision • University of Cincinnati VHDL-AMS simulator (SEAMS) • Infineon Technologies VHDL-AMS Environment • Analogy TheHDL Mixed Signal Simulator • FTL Systems VHDL-AMS Compiler/Simulator • LEDA VHDL-AMS Front-end tools • University of Southampton VHDL-AMS Analyzer • University of Frankfurt Java VHDL-AMS Parser • Models: • http://www.ececs.uc.edu/~dpl/