Microprogram VHDL

1. Microprogram VHDL ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering 445_12

2. Microinstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0 F1 F2 F3 F4 IR 445_12

3. Microprogram Controller IR DCD uAR Control Store F0 F4 uIR DCD ... Control Signals 445_12

4. Control Store entity ROM64x16 generic(MEM_INIT : MEM64x16); port(ADDRESS : in std_logic_vector(5 downto 0); Read : in std_logic; DATA_OUT : out std_logic_vector(15 downto 0)); end ROM64x16; 445_12

5. Microinstruction Encoding 445_12

6. Control Store Control_Store : ROM64x16 generic map ((X"04E4", -- 00 MAR <- [PC], PC <- [PC]+1 X" ", -- 01 MDR <- [[MEM([MAR])] X" ", -- 02 IR <- [MDR] X"4001", -- 03 Branch SRC_MODE X"83B2", -- 10 Y <- [REGS([SRC_REG])], Branch OPCODE others => X"0000")) port map ( ADDRESS => uAR, Read => ROM_Read, DATA_OUT => uIR ); 445_12

7. Microprogram Controller IR DCD uAR Control Store F0 F4 uIR DCD ... Control Signals 445_12

8. Microinstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0 F1 F2 F3 F4 IR 445_12

9. Control Signal Decoding entity DCD3to8 is port( I : in std_logic_vector(2 downto 0); D0 : out std_logic; D1 : out std_logic; D7 : out std_logic); end DCD3to8; alias F1 : std_logic_vector(2 downto 0) is uIR(9 downto 7); F1_DCD : DCD3to8 port map ( I => F1, D0 => open, D1 => PC_En_Out, D7 => REGS_Read ); 445_12

10. Microprogram Controller IR DCD uAR Control Store F0 F4 uIR DCD ... Control Signals 445_12

11. Microinstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0 F1 F2 F3 F4 IR 445_12

12. Microprogram Controller case F4 is when "00" => uAR <= F0; when "01" => uAR <= F0 or "00" & SRC_MODE & "00"; when "10" => uAR <= F0 or "000" & OPCODE; when "11" => uAR <= F0 or "000" & DST_MODE & "00"; when others => null; end case; 445_12

13. Homework 3 • Microprogrammed Control • Single-Bus Architecture • Addressing Modes • Same as HW2 • Testbench to Verify Registers and Memory 445_12

14. Single-Bus Architecture • 16 bit Datapath (from HW2) • 64 Word Memory • 4 General Purpose Registers • Instruction Storage • Main Memory 445_12

15. Single-Bus Architecture BUS A 6 6 MAR 6 PC MEM 1 MDR 2 IR 1 2 6 MUX MUX 2 Y 1 1 REGS A B ALU R Z 445_12

16. 00 MAR  [PC], PC <- [PC] + 1 01 MDR  [MEM([MAR])] 02 IR  [MDR] Instruction Fetch BUS A 6 6 MAR 6 PC MEM 1 MDR 2 IR 1 445_12

17. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OP SRC DST VALUE IR HW2/3 Instruction Encoding EA = Effective Address 445_12

18. SRC Control Flowchart Reg Direct 00 Reg Indir 01 0316 N N Y Y Y  [REGS([SRC_REG])] MAR  [REGS([SRC_REG])] 1016 1416 MDR  [MEM([MAR])] 1516 Y  [MDR] 1616 445_12

19. Microinstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0 F1 F2 F3 F4 uIR 445_12

20. Microinstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0 F1 F2 F3 F4 IR 445_12

21. Microinstruction Encoding 445_12

22. Test Program MEM : RAM64x16 generic map ((X"100D", -- 00 MOVE #NUM2,R0 X"184C", -- 01 MOVE NUM1,R1 X"0880", -- 02 MOVE (R0),R2 X"E000", -- 06 Halt X"000A", -- 0C NUM1 10 X"0007", -- 0D NUM2 7 others => X"0000")) -- xx-63 445_12

23. Simulation 445_12

24. HW3 Requirements • VHDL Package Descriptions • VHDL Control Architecture • Microprogram Control • Test Instructions from HW2 • VHDL Testbench • Verify Memory and Register Contents • Due in Class on Oct 20 445_12